參數(shù)資料
型號: MCIMX355AVM5BR2
廠商: Freescale Semiconductor
文件頁數(shù): 56/147頁
文件大?。?/td> 0K
描述: IC MPU I.MX35 400MAPBGA
標(biāo)準(zhǔn)包裝: 1,000
系列: i.MX35
核心處理器: ARM11
芯體尺寸: 32-位
速度: 532MHz
連通性: 1 線,CAN,EBI/EMI,以太網(wǎng),I²C,MMC,SPI,SSI,UART/USART,USB OTG
外圍設(shè)備: DMA,I²S,LCD,POR,PWM,WDT
輸入/輸出數(shù): 96
程序存儲器類型: ROMless
RAM 容量: 128K x 8
電壓 - 電源 (Vcc/Vdd): 1.33 V ~ 1.47 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 400-LFBGA
包裝: 帶卷 (TR)
i.MX35 Applications Processors for Automotive Products, Rev. 10
Freescale Semiconductor
16
4.3
Supply Power-Up/Power-Down Requirements and Restrictions
This section provides power-up and power-down sequence guidelines for the i.MX35 processor.
CAUTION
Any i.MX35 board design must comply with the power-up and power-down
sequence guidelines as described in this section to guarantee reliable
operation of the device. Any deviation from these sequences can result in
irreversible damage to the i.MX35 processor (worst-case scenario).
Stop
VDD1,2,3,4 = 1.1 V (min.)
ARM is in wait for interrupt mode.
MAX is halted
L2 cache is kept powered.
L2 cache control logic off.
AWB enabled.
MCU PLL is off.
PER PLL is off.
All clocks are gated off.
OSC 24 MHz is on
OSC audio is off
RNGC internal osc is off
1.1
mA
77
mA
400
A
2.2
mA
1.2
mA
2.2
mA
Static
VDD1,2,3,4 = 1.1 V (min.)
ARM is in wait for interrupt mode.
MAX is halted
L2 cache is kept powered.
L2 cache control logic off.
AWB enabled.
MCU PLL is off.
PER PLL is off.
All clocks are gated off.
OSC 24MHz is on
OSC audio is off
RNGC internal osc is off
820
A
72
mA
50
A
1.7
mA
24
A
35
A
Note: Typical column: TA = 25
°C
Note: Maximum column: TA = 85
°C
Table 10. i.MX35 Power Modes (continued)
Power
Mode
Description
QVCC (ARM/L2
Peripheral)
MVDD/PVDD
OSC24M_VDD
OSC_AUDO_VDD
Typ.
Max.
Typ.
Max.
Typ.
Max.
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