參數(shù)資料
型號: MCM16Y1BGCFT16
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, MROM, MICROCONTROLLER, PQFP160
封裝: QFP-160
文件頁數(shù): 124/138頁
文件大?。?/td> 784K
代理商: MCM16Y1BGCFT16
MOTOROLA
MC68HC16Y1
86
MC68HC16Y1TS/D
When GPT pins are used as an 8-bit port, DDRGP determines whether pins are input or output and
PORTGP holds the 8-bit data.
DDRGP[7:0] — Port GP Data Direction Register
0 = Input only
1 = Output
When PORTGP is used for general-purpose I/O, each bit in DDRGP determines whether the corre-
sponding PORTGP bit is input or output.
All OC outputs can be controlled by the action of OC1. OC1M contains a mask that determines which
pins are affected, and OC1D determines what the outputs are.
OC1M[5:1] — OC1 Mask Field
0 = Corresponding output compare pin is not affected by OC1 compare.
1 = Corresponding output compare pin is affected by OC1 compare.
OC1M[5:1] correspond to OC[5:1].
OC1D[5:1] — OC1 Data Field
0 = If OC1 mask bit is set, clear the corresponding output compare pin on OC1 match.
1 = If OC1 mask bit is set, set the corresponding output compare pin on OC1 match.
OC1D[5:1] correspond to OC[5:1].
TCNT — Timer Counter Register
$YFF90A
TCNT is the 16-bit free-running counter associated with the input capture, output compare, and pulse
accumulator functions of the GPT module.
PACTL enables the pulse accumulator and selects either event counting or gated mode. In event count-
ing mode, PACNT is incremented each time an event occurs. In gated mode, it is incremented by an
internal clock.
PAIS — PAI Pin State (Read-Only)
PAEN — Pulse Accumulator System Enable
0 = Pulse accumulator disabled
1 = Pulse accumulator enabled
DDRGP/PORTGP — Port GP Data Direction Register/Port GP Data Register
$YFF906
15
8
7
0
DDRGP
PORTGP
RESET:
0
OC1M/OC1D — OC1 Action Mask Register/OC1 Action Data Register
$YFF908
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0C1M
0
0C1D
0
RESET:
0
PACTL/PACNT — Pulse Accumulator Control Register/Counter
$YFF90C
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PAIS
PAEN
PAMOD
PEDGE PCLKS
I4/O5
PACLK
PULSE ACCUMULATOR COUNTER
RESET:
U
0
U
0
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