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MOTOROLA
Revision 8.0 - 28 November 2001 : MCM20027
48
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
ImageMOS
SFRS mode. Please refer to
Figure 14, on page 20
for
a timing diagram of this mode.
The
sp
bit is used to define whether SOF is active high
or low. SOF is active high in default.
The
ve
bit is used to determine whether VCLK is output
at the beginning of all the rows including virtual frame
rows or for the WOI rows only. The default is WOI only.
The
vp
bit is used to define whether VCLK is active high
or low. VCLK is active high in default.
The
he
bit is used to determine whether HCLK is output
continuously or for the WOI pixels only. The default is
WOI only.
The
hp
bit is used to define whether HCLK is active high
or low. HCLK is active high in default.
The
hm
bit is used to define HCLK is toggled or wheth-
erwhether it is continuously output.
The
Sub-sample Control Register; Table 30
, is used to
define what pixels of the WOI are read and the method
they are read.
Using the
cm
bit, the user can sample the pixel array in
either monochrome or Bayer pattern color space. This
means that when sampling the rows or columns, the set
of pixels read will be gathered as individual pixels
(monochrome) or in color tiles of pixels (Bayer pattern).
The pixels will be read in monochrome mode in default.
The row sub sampling rate is defined by
rf
[1:0] while the
column sub sampling rate is defined by
cf
[1:0]. The pix-
el array is fully sampled in default.
Address
40
h
Capture Mode Control
Default
2A
h
msb (7)
6
5
4
3
2
1
lsb (0)
FUO
cms
sp
ve
vp
he
hp
hm
Bit
Number
Function
Description
Reset
State
7
FUO
Factory Use Only
0
b
6
Capture
Mode
0
b
= Continuos Frame Rolling Shutter
1
b
= Single Frame Rolling Shutter
0
b
5
SOF
Phase
1
b
= SOF active high
0
b
= SOF active low
1
b
4
VCLK
Enable
1
b
= All virtual frame rows
0
b
= Window of Interest rows only
0
b
3
VCLK
Phase
1
b
= Active high
0
b
= Active low
1
b
2
HCLK
Enable
1
b
= Continuous
0
b
= Window of Interest Pixels only
0
b
1
HCLK
Phase
1
b
= Active high
0
b
= Active low
1
b
0
HCLK
Mode
1
b
= Continuous - envelope
0
b
= Toggles - like MCLK
0
b
Table 29. Capture Mode Control Register