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參數(shù)資料
| 型號： | MCM32A964SG33 |
| 廠商： | MOTOROLA INC |
| 元件分類： | DRAM |
| 英文描述： | 128KB/256KB Secondary Cache Module With Tag, Valid, and Dirty for i486 Processor Systems |
| 中文描述： | 64K X 32 CACHE TAG SRAM MODULE, 25 ns, DMA112 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大小： | 169K |
| 代理商： | MCM32A964SG33 |
MCM32A732/764
MCM32A832/864
MCM32A932/964
8
MOTOROLA FAST SRAM
WRITE CYCLE 1
(W Controlled, See Notes 1, 2, and 3)
Data
Tag/Valid
Dirty
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Write Cycle Time
tAVAV
tAVWL
30
—
30
—
30
—
ns
4
Address Setup Time
(A4 – A5)
(A6 – A19)
2
10
—
—
—
2
—
—
—
10
—
—
ns
Address Valid to End of Write
tAVWH
tWLWH,
tWLEH
20
—
10
—
20
—
ns
Write Pulse Width
12
—
12
—
12
—
ns
Data Setup to Write Time
tDVWH
tWHDX
tWLQZ
tWHQX
tWHAX
8
—
6
—
8
—
ns
Data Hold from Write Time
0
—
0
—
0
—
ns
Write Low to Output High–Z
0
8
0
6
0
8
ns
6,7,8
Write High to Output Active
4
—
4
—
4
—
ns
6,7,8
Write Recovery Time
0
—
0
—
0
—
ns
NOTES:
1. A write occurs during the overlap of E low and W low.
2. E = Exx, ET; W = Wxx, WT, WA; G = GA, GB
3. If G goes low coincident with or after W goes low, the output will remain in a high impedance state.
4. All timings are referenced from the last valid address to the first transitioning address.
5. If G
≥
VIH, the output will remain in a high impedance state.
6. At any given voltage and temperature, tWLQZ (max) is less than tWHQX (min), both for a given device and from device to device.
7. Transition is measured
±
500 mV from steady–state voltage with load of Figure 1B.
8. This parameter is sampled and not 100% tested.
WRITE CYCLE 1
(W Controlled, See Notes 1 and 2)
DATA VALID
tDVWH
tAVWL
tAVWH
tAVAV
tWHAX
tWLWH
tWLEH
tWHDX
tWLQZ
tWHQX
HIGH–Z
HIGH–Z
A (ADDRESS)
W (WRITE ENABLE)
E (CHIP ENABLE)
Q (DATA OUT)
D (DATA IN)
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