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參數(shù)資料
| 型號： | MCM62Y308 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Synchronous Line Buffer:8K x 8 Bit Fast Static Dual Ported Memory |
| 中文描述： | 同步線緩沖區(qū)器：8K × 8位快速靜態(tài)雙端口存儲器 |
| 文件頁數(shù)： | 5/16頁 |
| 文件大小： | 257K |
| 代理商： | MCM62Y308 |
MCM62Y308
5
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(TA = 0 to + 70
°
C, Unless Otherwise Noted)
Input Pulse Levels
Input Rise/Fall Time
Input Timing Measurement Reference Level
0 to 3.0 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 ns
1.5 V
. . . . . . . . . . . . . . .
Output Timing Reference Level
Output Load
. . . . . . . . . . . . .
1.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . .
Terminated 50 Ohm Transmission Line
READ/WRITE CYCLE TIMING
MCM62Y308–17
Parameter
Symbol
Min
Max
Unit
Notes
Cycle Time
tKHKH
tKHKL
tKLKH
tKHQV
tKHRFV
tKHQZ
tGLQV
tGHQZ
tREVKH
tWEVKH
tWRVKH
tRRRVKH
tWRRVKH
tGVKH
tRRVKH
tDVKH
tKHREX
tKHWEX
tKHRRX
tKHWRX
tKHRRRX
tKHWRRX
tKHGX
tKHDX
22
—
ns
Clock High Time
9
—
ns
Clock Low Time
9
—
ns
Clock High to Output Valid
5
17
ns
Clock High to Roll–Over Flag Valid
5
11
ns
Clock High to Output High–Z
5
15
ns
1
Output Enable Low to Output Valid
3
10
ns
2, 4
Output Enable High to Output High–Z
0
5
ns
2, 3, 4
Setup Times:
RE
WE
WR
RRR
WRR
G
RR
Data In
2
3
1
—
—
—
ns
5
6
5
Hold Times:
RE
WE
RR
WR
RRR
WRR
G
Data In
2
—
ns
5
6
NOTES:
1. The outputs High–Z from a clock high edge when the upper three bits of the Read Address Counter do not match the 3 ID Expansion bits.
2. G is a don’t care when the three ID expansion bits do not match the upper three bits of the Read Address Counter.
3. tGLQV and tGHQZ only apply when G is programmed as Asynchronous. (See TAP LDCONT instruction.)
4. Transition is measured
±
500 mV from steady–state voltage. This parameter is sampled and not 100% tested. At any given voltage and
temperature, tGHQZ max is less than tGLQV min for a given device and from device to device.
5. This is a synchronous device. All inputs must meet the specified setup and hold times for
ALL
rising edges of Clock except for G when it is
programmed to be asynchronous.
6. tGVKH and tKHGX only apply when G is programmed as synchronous.
AC TEST LOADS
Figure 1A
Figure 1B
The table of timing values shows either a
minimum or a maximum limit for each param-
eter. Input requirements are specified from
the external system point of view. Thus, ad-
dress setup time is shown as a minimum
since the system must supply at least that
much time (even though most devices do not
require it). On the other hand, responses from
the memory are specified from the device
point of view. Thus, the access time is shown
as a maximum since the device never pro-
vides data later than that time.
TIMING LIMITS
OUTPUT
Z0 = 50
RL = 50
VL = 1.5 V
5 pF
+ 5 V
OUTPUT
255
480
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| MCM62Y308J17 | Synchronous Line Buffer:8K x 8 Bit Fast Static Dual Ported Memory |
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相關(guān)代理商/技術(shù)參數(shù) |
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| MCM62Y308J17 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Synchronous Line Buffer:8K x 8 Bit Fast Static Dual Ported Memory |
| MCM6323A | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:64K x 16 Bit 3.3 V Asynchronous Fast Static RAM |
| MCM6323ATS10 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:64K x 16 Bit 3.3 V Asynchronous Fast Static RAM |
| MCM6323ATS10R | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:64K x 16 Bit 3.3 V Asynchronous Fast Static RAM |
| MCM6323ATS12 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:64K x 16 Bit 3.3 V Asynchronous Fast Static RAM |
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