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參數(shù)資料
| 型號： | MCM6343YJ15 |
| 廠商： | MOTOROLA INC |
| 元件分類： | SRAM |
| 英文描述： | 256K x 15 Bit 3.3 V Asynchronous Fast Static RAM |
| 中文描述： | 256K X 16 STANDARD SRAM, 15 ns, PDSO44 |
| 封裝： | 0.400 INCH, SOJ-44 |
| 文件頁數(shù)： | 1/10頁 |
| 文件大?。?/td> | 169K |
| 代理商： | MCM6343YJ15 |
MCM6343
1
Motorola, Inc. 1998
Product Preview
256K x 16 Bit 3.3 V Asynchronous
Fast Static RAM
The MCM6343 is a 4,194,304–bit static random access memory organized as
262,144 words of 16 bits. Static design eliminates the need for external clocks
or timing strobes.
The MCM6343 is equipped with chip enable (E), write enable (W), and output
enable (G) pins, allowing for greater system flexibility and eliminating bus con-
tention problems. Separate byte enable controls (LB and UB) allow individual
bytes to be written and read. LB controls the lower bits DQ0 to DQ7, while UB
controls the upper bits DQ8 to DQ15.
The MCM6343 is available in a 400 mil, 44–lead small–outline SOJ package
and a 44–lead TSOP Type II package.
Single 3.3 V
±
0.3 V Power Supply
Fast Access Time: 12/15 ns
Equal Address and Chip Enable Access Time
All Inputs and Outputs are TTL Compatible
Data Byte Control
Fully Static Operation
Power Operation: 250/240/230 mA Maximum, Active AC
Commercial and Standard Industrial Temperature Option: – 40 to + 85
°
C
BLOCK DIAGRAM
OUTPUT
ENABLE
BUFFER
ADDRESS
BUFFERS
WRITE
ENABLE
BUFFER
BYTE
ENABLE
BUFFER
ROW
DECODER
COLUMN
DECODER
256K x 16
BIT
MEMORY
ARRAY
HIGH
BYTE
OUTPUT
BUFFER
8
HIGH
BYTE
WRITE
DRIVER
LOW
BYTE
OUTPUT
BUFFER
LOW
BYTE
WRITE
DRIVER
SENSE
AMPS
G
W
LB
8
8
8
8
8
8
8
9
A
CHIP
ENABLE
BUFFER
E
UB
9
HIGH BYTE OUTPUT ENABLE
LOW BYTE OUTPUT ENABLE
HIGH BYTE WRITE ENABLE
LOW BYTE WRITE ENABLE
16
18
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
Order this document
by MCM6343/D
SEMICONDUCTOR TECHNICAL DATA
MCM6343
YJ PACKAGE
400 MIL SOJ
CASE 919–01
PIN ASSIGNMENT
A0 – A17
E
. . . . . . . . . . . . . . . . . . . . . . . . .
W
. . . . . . . . . . . . . . . . . . . . . . .
G
. . . . . . . . . . . . . . . . . . . . . .
UB
. . . . . . . . . . . . . . . . . . . . . . . .
LB
. . . . . . . . . . . . . . . . . . . . . . . . .
DQ0 – DQ15
. . . . . . . . . .
VDD
. . . . . . . . . . . . . .
VSS
. . . . . . . . . . . . . . . . . . . . . . . . . .
NC
. . . . . . . . . . . . . . . . . . . . .
Address Input
Chip Enable
Write Enable
Output Enable
Upper Byte
Lower Byte
Data Input/Output
+ 3.3 V Power Supply
. . . . . . . . . . . . . . . . .
Ground
No Connection
PIN NAMES
5
4
3
2
1
10
9
8
7
6
11
12
13
14
15
16
17
18
19
20
21
22
36
35
37
38
39
40
41
42
43
44
34
33
E
A
A
A
A
A
DQ1
DQ2
DQ0
VDD
VSS
DQ3
UB
G
A
A
A
DQ12
DQ13
DQ14
VSS
VDD
DQ15
LB
25
24
23
26
27
28
29
30
31
32
DQ8
NC
DQ9
DQ10
DQ11
A
A
A
A
A
W
A
DQ6
DQ7
DQ5
DQ4
A
A
A
A
TS PACKAGE
TSOP TYPE II
CASE 924A–02
REV 2
2/10/98
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