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參數(shù)資料
| 型號： | MCM63D736 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 128K x 36 Bit Synchronous Dual I/O, Dual Address SRAM(128K x 36 Bit同步雙I/O口,雙地址靜態(tài)存儲器) |
| 中文描述： | 128K的× 36位同步雙的I / O，雙地址的SRAM（128K的× 36位同步雙的I / O口，雙地址靜態(tài)存儲器） |
| 文件頁數(shù)： | 5/16頁 |
| 文件大小： | 126K |
| 代理商： | MCM63D736 |
MCM63D736
5
MOTOROLA FAST SRAM
TRUTH TABLE
(See Notes 1 through 6)
Operation
No.
Input at tn Clock
WX
E1X
E2X
E1Y
E2Y
WY
PTX
PTY
Operation
1
H
X
H
X
X
X
X
X
Deselected
2
X
L
X
L
X
X
X
X
Deselected
3
L
H
X
X
L
X
X
X
Write X Port
4
X
X
L
H
X
L
X
X
Write Y Port
5
L
H
L
H
X
X
L
X
Pass–Through X to Y
6
L
H
L
H
X
X
X
L
Pass–Through Y to X
7
L
H
X
X
H
X
H
H
Read X
8
X
X
L
H
X
H
H
H
Read Y
NOTES:
1. L = Logic Low; H = Logic High; X = Don’t Care.
2. GX/GY must be negated during write and pass–through cycles.
3. Operation numbers 3 – 6 can be used in any combination.
4. Operation numbers 4 and 7, 3 and 8, 7 and 8 can be combined.
5. Operation number 5 can not be combined with operation number 7 or 8 because pass–through takes precedence over a read operation.
6. Operation number 6 can not be combined with operation number 7 or 8 because pass–through takes precedence over a read operation.
K
ADDRESS & CONTROL
VALID
tn
tn + 1
VALID
DATA INPUT D
VALID
DATA OUTPUT Q
PIPELINED READ ACCESS
PASS–THROUGH
ABSOLUTE MAXIMUM RATINGS
(See Notes)
Rating
Symbol
Value
Unit
Power Supply Voltage
VDD
Vin, Vout
–0.5 to 4.6
V
Voltage Relative to VSS for Any Pin
Except VDD
–0.5 to VDD + 0.5
V
Output Current
Iout
PD
Tbias
Tstg
±
20
mA
Package Power Dissipation
1.6
W
Temperature Under Bias
–10 to 85
°
C
Storage Temperature — Plastic
–55 to 125
°
C
NOTES:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED
OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
2. Power dissipation capability is dependent upon package characteristics and use
environment. See Package Thermal Characteristics.
This is a synchronous device. All syn-
chronous inputs must meet specified setup and
hold times with stable logic levels for
ALL
rising edges of clock (K) while the device is
selected.
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to these high–impedance
circuits.
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