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參數(shù)資料
| 型號： | MCM63D736 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 128K x 36 Bit Synchronous Dual I/O, Dual Address SRAM(128K x 36 Bit同步雙I/O口,雙地址靜態(tài)存儲器) |
| 中文描述： | 128K的× 36位同步雙的I / O，雙地址的SRAM（128K的× 36位同步雙的I / O口，雙地址靜態(tài)存儲器） |
| 文件頁數(shù)： | 7/16頁 |
| 文件大?。?/td> | 126K |
| 代理商： | MCM63D736 |
MCM63D736
7
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V
±
5%, TA = 0
°
to 70
°
C, Unless Otherwise Noted)
Input Timing Measurement Reference Level
Input Pulse Levels
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time
. . . . . . . . . . . . . . . . . . . . . .
1.5 V
. . . . . . . . . . . . . . .
0 to 3.0 V
1 V/ns (20% to 80%)
Output Timing Reference Level
Output Load
. . . . . . . . . . . . . . . . . .
1.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 1 Unless Otherwise Noted
READ/WRITE CYCLE TIMING
(See Notes 1, 2, and 3)
MCM63D736–133
MCM63D736–100
MCM63D736–83
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Cycle Time
tKHKH
tKHQV
tKLKH
tKHKL
tKHQX1
tKHQX2
tKHQZ
tGLQV
7.5
—
10
—
12
—
ns
1
Clock Access Time
—
4
—
5
—
6
ns
Clock Low Pulse Width
3
—
4
—
4
—
ns
Clock High Pulse Width
3
—
4
—
4
—
ns
Clock High to Data Output Active
0
—
0
—
0
—
ns
Clock High to Data Output Invalid
1
—
1
—
1
—
ns
Clock High to Data Output High–Z
—
3
—
3
—
4
ns
2
Output Enable Low to Data Output
Valid
—
4
—
5
—
6
ns
Output Enable Low to Data Output
Low–Z
tGLQX
0
—
0
—
0
—
ns
Output Enable High to Data Output
High–Z
tGHQZ
—
3
—
3
—
5
ns
2
Setup Times:
AWR0 – AWR16
ARD0 – ARD16
W
PT
E1X, E2X, E1Y, E2Y
D0 – D35
tAVKH
tAVKH
tWVKH
tPTVKH
tEVKH
tDVKH
1.5
—
1.5
—
2.5
—
ns
3
Hold Times:
AWR0 – AWR16
ARD0 – ARD16
W
PT
E1X, E2X, E1Y, E2Y
D0 – D35
tKHAX
tKHAX
tKHWX
tKHPTX
tKHEX
tKHDX
0.5
—
0.5
—
0.5
—
ns
3
NOTES:
1. All read and write cycles are referenced from K.
2. This parameter is sampled and not 100% tested.
3. This is a synchronous device. All synchronous inputs must meet the specified setup and hold times with stable logic levels for
ALL
rising
edges of clock (K) while the device is selected.
OUTPUT
Z0 = 50
RL = 50
VL = 1.5 V
Figure 1. AC Test Load
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| MCM63D736TQ100 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:128K x 36 Bit Synchronous Dual I/O, Dual Address SRAM |
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