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參數(shù)資料
| 型號： | MCM6709ARJ7R2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | SRAM |
| 英文描述： | 64K x 4 Bit Static RAM |
| 中文描述： | 64K X 4 STANDARD SRAM, 7 ns, PDSO28 |
| 封裝： | 0.300 INCH, PLASTIC, SOJ-28 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大小： | 102K |
| 代理商： | MCM6709ARJ7R2 |
MCM6709BR
1
Motorola, Inc. 1997
Product Preview
64K x 4 Bit Static RAM
The MCM6709BR is a 262,144 bit static random access memory organized as
65,536 words of 4 bits. Static design eliminates the need for external clocks or
timing strobes.
Output enable (G) is a special control feature that provides increased system
flexibility and eliminates bus contention problems.
The MCM6709BR meets JEDEC standards and is available in a revolutionary
pinout 300 mil, 28 lead plastic surface–mount SOJ package.
Single 5 V
±
10% Power Supply
Fully Static — No Clock or Timing Strobes Necessary
All Inputs and Outputs are TTL Compatible
Center Power and I/O Pins for Reduced Noise
Three State Outputs
Fast Access Times:
MCM6709BR–6 = 6 ns
MCM6709BR–7 = 7 ns
MCM6709BR–8 = 8 ns
BLOCK DIAGRAM
G
INPUT
DATA
CONTROL
MEMORY MATRIX
512 ROWS x 128 x 4
COLUMNS
COLUMN I/O
COLUMN DECODER
DQ
DQ
E
W
ROW
DECODER
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.
Order this document
by MCM6709BR/D
SEMICONDUCTOR TECHNICAL DATA
PIN ASSIGNMENT
MCM6709BR
A
W
G
E
DQ
VCC
VSS
NC
Address Inputs
Write Enable
Output Enable
Chip Enable
Data Input/Output
+ 5 V Power Supply
. . . . . . . . . . . . . . . . . . .
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Ground
No Connection
PIN NAMES
J PACKAGE
300 MIL SOJ
CASE 810B–03
5
4
3
2
1
10
9
8
7
6
11
12
13
14
20
21
22
23
24
25
26
19
27
28
18
17
16
15
VCC
A
A
A
A
A
VSS
DQ
E
A
A
A
DQ
W
G
A
A
A
A
A
A
A
NC
DQ
VSS
VCC
DQ
A
All power supply and ground pins must
be connected for proper operation of the
device.
REV 2
3/17/97
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