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參數(shù)資料
| 型號(hào)： | MCM6709ARJ7R2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | SRAM |
| 英文描述： | 64K x 4 Bit Static RAM |
| 中文描述： | 64K X 4 STANDARD SRAM, 7 ns, PDSO28 |
| 封裝： | 0.300 INCH, PLASTIC, SOJ-28 |
| 文件頁(yè)數(shù)： | 5/7頁(yè) |
| 文件大?。?/td> | 102K |
| 代理商： | MCM6709ARJ7R2 |
MCM6709BR
5
MOTOROLA FAST SRAM
WRITE CYCLE 1
(W Controlled, See Notes 1 and 2)
MCM6709BR–6
MCM6709BR–7
MCM6709BR–8
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Write Cycle Time
tAVAV
tAVWL
tAVWH
tWLWH
tWLEH
6
—
7
—
8
—
ns
3
Address Setup Time
0
—
0
—
0
—
ns
Address Valid to End of Write
6
—
7
—
8
—
ns
Write Pulse Width
6
—
7
—
8
—
ns
Data Valid to End of Write
tDVWH
tWHDX
tWLQZ
tWHQX
tWHAX
3
—
3.5
—
3.5
—
ns
Data Hold Time
0
—
0
—
0
—
ns
Write Low to Data High–Z
—
3.5
—
3.5
—
3.5
ns
4, 5, 6
Write High to Output Active
3
—
3
—
3
—
ns
4, 5, 6
Write Recovery Time
0
—
0
—
0
—
ns
NOTES:
1. A write occurs during the overlap of E low and W low.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. All write cycle timing is referenced from the last valid address to the first transitioning address.
4. Transition is measured 200 mV from steady state voltage with load of Figure 1b.
5. This parameter is sampled and not 100% tested.
6. At any given voltage and temperature, tWLQZ max is less than tWHQX min both for a given device and from device to device.
WRITE CYCLE 1
DATA VALID
HIGH–Z
HIGH–Z
tAVAV
tAVWH
tWHAX
tWHDX
tWHQX
tWLWH
tAVWL
tDVWH
tWLQZ
A (ADDRESS)
E (CHIP ENABLE)
W (WRITE ENABLE)
D (DATA IN)
Q (DATA OUT)
tWLEH
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