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參數(shù)資料
| 型號： | MCM67B618A |
| 廠商： | Motorola, Inc. |
| 英文描述： | 64K x 18 Bit BurstRAM Synchronous Fast Static RAM |
| 中文描述： | 64K的× 18位BurstRAM同步快速靜態(tài)存儲器 |
| 文件頁數(shù)： | 1/12頁 |
| 文件大?。?/td> | 155K |
| 代理商： | MCM67B618A |
MCM67B618A
1
MOTOROLA FAST SRAM
Motorola, Inc. 1996
64K x 18 Bit BurstRAM
Synchronous Fast Static RAM
With Burst Counter and Self–Timed Write
The MCM67B618A is a 1,179,648 bit synchronous fast static random access
memory designed to provide a burstable, high–performance, secondary cache
for the i486
and Pentium
microprocessors. It is organized as 65,536 words
of 18 bits. The device integrates input registers, a 2–bit counter, high speed
SRAM, and high drive capability outputs onto a single monolithic circuit for re-
duced parts count implementation of cache data RAM applications. Synchro-
nous design allows precise cycle control with the use of an external clock (K).
BiCMOS circuitry reduces the overall power consumption of the integrated func-
tions for greater reliability.
Addresses (A0 – A15), data inputs (D0 – D17), and all control signals
except output enable (G) are clock (K) controlled through positive–edge–
triggered noninverting registers.
Bursts can be initiated with either address status processor (ADSP) or
address status cache controller (ADSC) input pins. Subsequent burst
addresses can be generated internally by the MCM67B618A (burst
sequence imitates that of the i486 and Pentium) and controlled by the burst
address advance (ADV) input pin. The following pages provide more de-
tailed information on burst controls.
Write cycles are internally self–timed and are initiated by the rising edge
of the clock (K) input. This feature eliminates complex off–chip write pulse
generation and provides increased flexibility for incoming signals.
Dual write enables (LW and UW) are provided to allow individually write-
able bytes. LW controls DQ0 – DQ8 (the lower bits), while UW controls
DQ9 – DQ17 (the upper bits).
This device is ideally suited for systems that require wide data bus
widths and cache memory. See Figure 2 for applications information.
Single 5 V
±
5% Power Supply
Fast Access Times: 9/10/12 ns Max
Byte Writeable via Dual Write Enables
Internal Input Registers (Address, Data, Control)
Internally Self–Timed Write Cycle
ADSP, ADSC, and ADV Burst Control Pins
Asynchronous Output Enable Controlled Three–State Outputs
Common Data Inputs and Data Outputs
3.3 V I/O Compatible
High Board Density 52–Lead PLCC Package
BurstRAM is a trademark of Motorola, Inc.
i486 and Pentium are trademarks of Intel Corp.
10
11
9
8
DQ9
DQ10
VCC
VSS
DQ5
DQ8
DQ7
12
13
15
16
14
17
18
20
19
37
36
38
34
35
42
41
43
39
40
45
44
46
21 22 23 24 25 26 27 28 29 30 31 32 33
7
6
5 4
3 2
1 52 51 50 49 4847
DQ6
DQ4
DQ3
DQ2
VSS
VCC
DQ1
DQ0
VCC
VSS
DQ11
DQ12
DQ13
DQ14
VSS
VCC
DQ15
DQ16
DQ17
A
A
E
U
K
A
A
A
L
G
A
A
A
A
A
A
A
A
A
V
A
A
V
A
A
A
All power supply and ground pins must be
connected for proper operation of the device.
PIN NAMES
A0 – A15
K
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADV
. . . . . . . . . . . .
LW
. . . . . . . . . . . .
UW
. . . . . . . . . . . .
ADSC
Controller Address Status
. . . . . . . . .
ADSP
Processor Address Status
. . . . . . . . .
E
. . . . . . . . . . . . . . . . . . . . . . . . .
G
. . . . . . . . . . . . . . . . . . . . . .
DQ0 – DQ17
. . . . . . . . . .
VCC
. . . . . . . . . . . . . . . .
VSS
. . . . . . . . . . . . . . . . . . . . . . . . . .
NC
. . . . . . . . . . . . . . . . . . . . .
Address Inputs
. . . . . . . . . . . . . . . .
Clock
Burst Address Advance
Lower Byte Write Enable
Upper Byte Write Enable
Chip Enable
Output Enable
Data Input/Output
+ 5 V Power Supply
Ground
No Connection
PIN ASSIGNMENTS
Order this document
by MCM67B618A/D
SEMICONDUCTOR TECHNICAL DATA
MCM67B618A
FN PACKAGE
PLASTIC
CASE 778–02
REV 2
11/5/96
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| MCM67Q909ZP12 | Circular Connector; Body Material:Aluminum; Series:PT07; Number of Contacts:3; Connector Shell Size:8; Connecting Termination:Solder; Circular Shell Style:Jam Nut Receptacle; Circular Contact Gender:Socket; Insert Arrangement:8-3 |
| MCM67Q909ZP12R | Circular Connector; Body Material:Aluminum; Series:PT07; Number of Contacts:4; Connector Shell Size:8; Connecting Termination:Solder; Circular Shell Style:Jam Nut Receptacle; Circular Contact Gender:Pin; Insert Arrangement:8-4 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MCM67B618AFN10 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:64K x 18 Bit BurstRAM Synchronous Fast Static RAM |
| MCM67B618AFN12 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:64K x 18 Bit BurstRAM Synchronous Fast Static RAM |
| MCM67B618AFN9 | 制造商:Motorola Inc 功能描述:Synchronous SRAM, 64K x 18, 52 Pin, Plastic, PLCC |
| MCM67B618AFN9R2 | 制造商:Motorola Inc 功能描述:64K X 18 CACHE SRAM, 9 ns, PQCC52 |
| MCM67B618B | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:64K x 18 Bit BurstRAM Synchronous Fast Static RAM With Burst Counter and Self-Timed Write |
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