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參數(shù)資料
| 型號(hào)： | MCM67B618AFN10 |
| 廠商： | MOTOROLA INC |
| 元件分類： | SRAM |
| 英文描述： | 64K x 18 Bit BurstRAM Synchronous Fast Static RAM |
| 中文描述： | 64K X 18 CACHE SRAM, 10 ns, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁(yè)數(shù)： | 5/12頁(yè) |
| 文件大?。?/td> | 155K |
| 代理商： | MCM67B618AFN10 |
MCM67B618A
5
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V
±
5%, TA = 0 to + 70
°
C, Unless Otherwise Noted)
Input Timing Measurement Reference Level
Input Pulse Levels
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 V
. . . . . . . . . . . . . . .
0 to 3.0 V
3 ns
Output Timing Reference Level
Output Load
. . . . . . . . . . . . .
1.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . .
See Figure 1a Unless Otherwise Noted
READ/WRITE CYCLE TIMING
(See Notes 1, 2, 3, and 4)
MCM67B618A–9
MCM67B618A–10
MCM67B618A–12
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Cycle Time
tKHKH
tKHQV
tGLQV
tKHQX1
tKHQX2
tGLQX
tGHQZ
tKHQZ
tKHKL
tKLKH
tAVKH
tADSVKH
tDVKH
tWVKH
tADVVKH
tEVKH
15
—
16.6
—
20
—
ns
Clock Access Time
—
9
—
10
—
12
ns
5
Output Enable to Output Valid
—
5
—
5
—
6
ns
Clock High to Output Active
6
—
6
—
6
—
ns
Clock High to Output Change
3
—
3
—
3
—
ns
Output Enable to Output Active
0
—
0
—
0
—
ns
Output Disable to Q High–Z
—
6
—
7
—
7
ns
6
Clock High to Q High–Z
3
6
3
7
—
7
ns
Clock High Pulse Width
5
—
5
—
6
—
ns
Clock Low Pulse Width
5
—
5
—
6
—
ns
Setup Times:
Address
Address Status
Data In
Write
Address Advance
Chip Enable
2.5
—
2.5
—
2.5
—
ns
7
Hold Times:
Address
Address Status
Data In
Write
Address Advance
Chip Enable
tKHAX
tKHADSX
tKHDX
tKHWX
tKHADVX
tKHEX
0.5
—
0.5
—
0.5
—
ns
7
NOTES:
1. In setup and hold times, W (write) refers to either one or both byte write enables LW and UW.
2. A read cycle is defined by UW and LW high or ADSP low for the setup and hold times. A write cycle is defined by LW or UW low and ADSP
high for the setup and hold times.
3. All read and write cycle timings are referenced from K or G.
4. G is a don’t care when UW or LW is sampled low.
5. Maximum access times are guaranteed for all possible i486 and Pentium external bus cycles.
6. Transition is measured
±
500 mV from steady–state voltage with load of Figure 1b. This parameter is sampled rather than 100% tested. At
any given voltage and temperature, tKHQZ max is less than tKHQZ1 min for a given device and from device to device.
7. This is a synchronous device. All addresses must meet the specified setup and hold times for
ALL
rising edges of K whenever ADSP or ADSC
is low, and the chip is selected. All other synchronous inputs must meet the specified setup and hold times for
ALL
rising edges of K when
the chip is enabled. Chip enable must be valid at each rising edge of clock for the device (when ADSP or ADSC is low) to remain enabled.
(a)
(b)
5 pF
+ 5 V
OUTPUT
480
255
OUTPUT
Z0 = 50
RL = 50
VL = 1.5 V
Figure 1. Test Loads
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