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參數(shù)資料
| 型號(hào)： | MCM67M618B |
| 廠商： | Motorola, Inc. |
| 英文描述： | 64K x 18 Bit BurstRAM Synchronous Fast Static RAM |
| 中文描述： | 64K的× 18位BurstRAM同步快速靜態(tài)存儲(chǔ)器 |
| 文件頁數(shù)： | 1/12頁 |
| 文件大?。?/td> | 166K |
| 代理商： | MCM67M618B |
MCM67M618B
1
MOTOROLA FAST SRAM
Motorola, Inc. 1997
Advance Information
64K x 18 Bit BurstRAM
Synchronous Fast Static RAM
With Burst Counter and Self–Timed Write
The MCM67M618B is a 1,179,648 bit synchronous static random access
memory designed to provide a burstable, high–performance, secondary cache
for the MC68040 and PowerPC
microprocessors. It is organized as 65,536
words of 18 bits, fabricated using Motorola’s high–performance silicon–gate
BiCMOS technology. The device integrates input registers, a 2–bit counter, high
speed SRAM, and high drive capability outputs onto a single monolithic circuit
for reduced parts count implementation of cache data RAM applications. Syn-
chronous design allows precise cycle control with the use of an external clock
(K). BiCMOS circuitry reduces the overall power consumption of the integrated
functions for greater reliability.
Addresses (A0 – A15), data inputs (DQ0 – DQ17), and all control sig-
nals, except output enable (G), are clock (K) controlled through posi-
tive–edge–triggered noninverting registers.
Bursts can be initiated with either transfer start processor (TSP) or
transfer start cache controller (TSC) input pins. Subsequent burst
addresses are generated internally by the MCM67M618B (burst
sequence imitates that of the MC68040) and controlled by the burst
address advance (BAA) input pin. The following pages provide more
detailed information on burst controls.
Write cycles are internally self–timed and are initiated by the rising
edge of the clock (K) input. This feature eliminates complex off–chip
write pulse generation and provides increased flexibility for incoming
signals.
Dual write enables (LW and UW) are provided to allow individually
writeable bytes. LW controls DQ0 – DQ8 (the lower bits), while UW
controls DQ9 – DQ17 (the upper bits).
This device is ideally suited for systems that require wide data bus
widths and cache memory.
Single 5 V
±
5% Power Supply
Fast Access Times: 9/10/12 ns Max
Byte Writeable via Dual Write Strobes
Internal Input Registers (Address, Data, Control)
Internally Self–Timed Write Cycle
TSP, TSC, and BAA Burst Control Pins
Asynchronous Output Enable Controlled Three–State Outputs
Common Data Inputs and Data Outputs
High Board Density 52–PLCC Package
3.3 V I/O Compatible
The PowerPC name is a trademark of IBM Corp., used under license therefrom.
This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.
Order this document
by MCM67M618B/D
SEMICONDUCTOR TECHNICAL DATA
MCM67M618B
FN PACKAGE
PLASTIC
CASE 778–02
PIN ASSIGNMENT
10
11
9
8
DQ9
DQ10
VCC
VSS
DQ5
DQ8
DQ7
12
13
15
16
14
17
18
20
19
37
36
38
34
35
42
41
43
39
40
45
44
46
21 22 23 24 25 26 27 28 29 30 31 32 33
7
6
5 4
3
2
1 52 51 50 49 48 47
DQ6
DQ4
DQ3
DQ2
VSS
VCC
DQ1
DQ0
VCC
VSS
DQ11
DQ12
DQ13
DQ14
VSS
VCC
DQ15
DQ16
DQ17
A
A
E
U
K
A
A
A
L
G
A
A
A
A
A
A
A
A
A
V
A
A
V
B
T
T
All power supply and ground pins must be con-
nected for proper operation of the device.
PIN NAMES
A0 – A15
K
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BAA
. . . . . . . . . . . .
LW
. . . . . . . . . . . .
UW
. . . . . . . . . . . .
TSP, TSC
. . . . . . . . . . . . . . . .
E
. . . . . . . . . . . . . . . . . . . . . . . . .
G
. . . . . . . . . . . . . . . . . . . . . .
DQ0 – DQ17
. . . . . . . . . .
VCC
. . . . . . . . . . . . . . . .
VSS
. . . . . . . . . . . . . . . . . . . . . . . . . .
Address Inputs
. . . . . . . . . . . . . . . .
Clock
Burst Address Advance
Lower Byte Write Enable
Upper Byte Write Enable
Transfer Start
Chip Enable
Output Enable
Data Input/Output
+ 5 V Power Supply
Ground
REV 1
7/15/97
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