- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379319 > MCM67M618B (Motorola, Inc.) 64K x 18 Bit BurstRAM Synchronous Fast Static RAM PDF資料下載
參數(shù)資料
| 型號： | MCM67M618B |
| 廠商： | Motorola, Inc. |
| 英文描述： | 64K x 18 Bit BurstRAM Synchronous Fast Static RAM |
| 中文描述： | 64K的× 18位BurstRAM同步快速靜態(tài)存儲器 |
| 文件頁數(shù)： | 2/12頁 |
| 文件大?。?/td> | 166K |
| 代理商： | MCM67M618B |
MCM67M618B
2
MOTOROLA FAST SRAM
EXTERNAL
ADDRESS
9
9
18
16
A15 – A2
DQ0 – DQ8
INTERNAL
ADDRESS
ADDRESS
REGISTERS
WRITE
REGISTER
ENABLE
REGISTER
DATA–IN
REGISTERS
BAA
K
TSP
TSC
A15 – A0
UW
LW
E
G
9
DQ9 – DQ17
9
9
9
A0
′
A1
′
A1
LOAD
D1
BINARY
COUNTER
D0
Q1
Q0
BURST LOGIC
A0
BLOCK DIAGRAM
(See Note)
OUTPUT
BUFFER
64K x 18
MEMORY
ARRAY
16
NOTE:
All registers are positive–edge triggered. The TSC or TSP signals control the duration of the burst and the start of the next
burst. When TSP is sampled low, any ongoing burst is interrupted and a read (independent of W and TSC) is performed
using the new external address. Alternatively, a TSP–initiated two cycle WRITE can be performed by asserting TSP and
a valid address on the first cycle, then negating both TSP and TSC and asserting LW and/or UW with valid data on the
second cycle (see Single Write Cycle in WRITE CYCLES timing diagram).
When TSC is sampled low (and TSP is sampled high), any ongoing burst is interrupted and a read or write (dependent on
W) is performed using the new external address. Chip enable (E) is sampled only when a new base address is loaded. After
the first cycle of the burst, BAA controls subsequent burst cycles. When BAA is sampled low, the internal address is
advanced prior to the operation. When BAA is sampled high, the internal address is not advanced, thus inserting a wait
state into the burst sequence accesses. Upon completion of a burst, the address will wrap around to its initial state.
See
BURST SEQUENCE TABLE
. Write refers to either or both byte write enables (LW, UW).
1,0
1,1
0,0
0,1
A1
′
, A0
′
=
NOTE: The external two values for A1 and A0
provide the starting point for the burst
sequence graph. The burst logic ad-
vances A1 and A0 as shown above.
BURST SEQUENCE GRAPH
(See Note)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MCM67M618BFN10 | 64K x 18 Bit BurstRAM Synchronous Fast Static RAM |
| MCM67M618BFN12 | 64K x 18 Bit BurstRAM Synchronous Fast Static RAM |
| MCM67M618BFN9 | 64K x 18 Bit BurstRAM Synchronous Fast Static RAM |
| MCM8A10SG15 | 16 Characters x 4 Lines, 5x7 Dot Matrix Character and Cursor |
| MCM8A10 | 1M x 8 Bit Fast Static RAM Module |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MCM67M618BFN10 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:64K x 18 Bit BurstRAM Synchronous Fast Static RAM |
| MCM67M618BFN12 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:64K x 18 Bit BurstRAM Synchronous Fast Static RAM |
| MCM67M618BFN9 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:64K x 18 Bit BurstRAM Synchronous Fast Static RAM |
| MCM67Q709A | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:128K x 9 Bit Separate I/O Synchronous Fast Static RAM |
| MCM67Q709AZP10 | 制造商:Motorola Inc 功能描述:Synchronous SRAM, 128K x 9, 86 Pin, Plastic, BGA |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。