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參數(shù)資料
| 型號： | MCM69R737A |
| 廠商： | Motorola, Inc. |
| 英文描述： | 4M-bit Synchronous Late Write Fast SRAM(4M位同步遲寫、快速靜態(tài)RAM) |
| 中文描述： | 4分位同步后寫入快速靜態(tài)存儲器（4分位同步遲寫，快速靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 4/20頁 |
| 文件大小： | 212K |
| 代理商： | MCM69R737A |
MCM69R737A
MCM69R819A
4
MOTOROLA FAST SRAM
MCM69R819A PIN DESCRIPTIONS
PBGA Pin Locations
Symbol
Type
Description
4K
CK
Input
Address, data in and control input register clock. Active high.
4L
CK
Input
Address, data in and control input register clock. Active low.
(a) 6D, 7E, 6F, 7G, 6H, 7K, 6L, 6N, 7P
(b) 1D, 2E, 2G, 1H, 2K, 1L, 2M, 1N, 2P
DQx
I/O
Synchronous Data I/O.
4F
G
Input
Output Enable: Asynchronous pin, active low.
2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, 5C,
6C, 4N, 4P, 2R, 6R, 2T, 3T, 5T, 6T
SA
Input
Synchronous Address Inputs: Registered on the rising clock edge.
5L, 3G
(a), (b)
SBx
Input
Synchronous Byte Write Enable: Enables writes to byte x in
conjunction with the SW input. Has no effect on read cycles, active
low.
4E
SS
Input
Synchronous Chip Enable: Registered on the rising clock edge, active
low.
4M
SW
Input
Synchronous Write: Registered on the rising clock edge, active low.
Writes all enabled bytes.
4U
TCK
Input
Test Clock (JTAG).
3U
TDI
Input
Test Data In (JTAG).
5U
TDO
Output
Test Data Out (JTAG).
2U
TMS
Input
Test Mode Select (JTAG).
7T
ZZ
Input
Enables sleep mode, active high.
4C, 2J, 4J, 6J, 4R, 5R
VDD
VDDQ
VSS
Supply
Core Power Supply.
1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U
Supply
Output Power Supply: provides operating power for output buffers.
3D, 5D, 3E, 5E, 3F, 5F, 5G, 3H, 5H,
3K, 5K, 3L, 3M, 5M, 3N, 5N, 3P, 5P, 3R
Supply
Ground.
4A, 1B, 2B, 4B, 6B, 7B, 1C, 7C,
2D, 4D, 7D, 1E, 6E, 2F, 1G, 4G, 6G,
2H, 4H, 7H, 3J, 5J, 1K, 6K, 2L, 7L, 6M, 2N,
7N, 1P, 6P, 1R, 7R, 1T, 4T, 6U
NC
—
No Connection: There is no connection to the chip.
Note: 3J and 5J are tied common.
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相關代理商/技術參數(shù) |
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| MCM69R737AZP7 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:4M Late Write LVTTL |
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