參數(shù)資料
型號(hào)： MCM69R737A
廠商： Motorola, Inc.
英文描述： 4M-bit Synchronous Late Write Fast SRAM(4M位同步遲寫(xiě)、快速靜態(tài)RAM)
中文描述： 4分位同步后寫(xiě)入快速靜態(tài)存儲(chǔ)器（4分位同步遲寫(xiě)，快速靜態(tài)內(nèi)存）
文件頁(yè)數(shù)： 7/20頁(yè)
文件大小： 212K
代理商： MCM69R737A
MCM69R737A
MCM69R819A
7
MOTOROLA FAST SRAM
CAPACITANCE
(f = 1.0 MHz, dV = 3.0 V, 0
°
C
≤
TA
≤
70
°
C, Periodically Sampled Rather Than 100% Tested)
Characteristic
Symbol
Typ
Max
Unit
Input Capacitance
Cin
CI/O
CCK
4
5
pF
Input/Output Capacitance
7
8
pF
CK, CK Capacitance
4
5
pF
AC OPERATING CONDITIONS AND CHARACTERISTICS
(0
°
C
≤
TA
≤
70
°
C, Unless Otherwise Noted)
Input Pulse Levels
Input Rise/Fall Time
Input Timing Measurement Reference Level
Output Timing Reference Level
0 to 3.0 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . .
1 V/ns (20% to 80%)
. . . . . . . . . . . . . . .
1.5 V
1.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Input Timing Reference Level
Clock Input Pulse Level
R
θ
JA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential Cross–Point
1.8 V to 2.1 V
. . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . .
TBD
READ/WRITE CYCLE TIMING
(See Note 1)
MCM69R737A–5
MCM69R819A–5
MCM69R737A–6
MCM69R819A–6
MCM69R737A–7
MCM69R819A–7
MCM69R737A–8
MCM69R819A–8
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Notes
Cycle Time
tKHKH
tKHKL
tKLKH
tKHQX1
5
—
6
—
7
—
8
—
ns
Clock High Pulse Width
2
—
2.4
—
2.8
—
3.2
—
ns
Clock Low Pulse Width
2
—
2.4
—
2.8
—
3.2
—
ns
Clock High to Output
Low–Z
1
—
1
—
1
—
1
—
ns
2,3
Clock High to Output
Valid
tKHQV
—
2.5
—
3
—
3.5
—
3.5
ns
Clock High to Output
Hold
tKHQX
0.5
—
0.5
—
0.5
—
0.5
—
ns
Clock High to Output
High–Z
tKHQZ
—
2.5
—
3
—
3.5
—
3.5
ns
2, 3
Output Enable Low to
Output Low–Z
tGLQX
0.5
—
0.5
—
0.5
—
0.5
—
ns
Output Enable Low to
Output Valid
tGLQV
—
2.5
—
3
—
3.5
—
3.5
ns
Output Enable to Output
Hold
tGHQX
0.5
—
0.5
—
0.5
—
0.5
—
ns
Output Enable High to
Output High–Z
tGHQZ
—
2.5
—
—
3.5
—
3.5
ns
2, 3
Setup Times:
Address
Data In
Chip Select
Write Enable
tAVKH
tDVKH
tSVKH
tWVKH
tKHAX
tKHDX
tKHSX
tKHWX
0.5
—
0.5
—
0.5
—
0.5
—
ns
Hold Times:
Address
Data In
Chip Select
Write Enable
1
—
1
—
1
—
1
—
ns
NOTES:
1. In no case may control input signals (e.g., SS) be operated with pulse widths less than the minimum clock input pulse width specifications
(e.g., tKHKL) or at frequencies that exceed the applied K clock frequency.
2. This parameter is sampled and not 100% tested.
3. Measured at
±
200 mV from steady state.
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