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參數(shù)資料
| 型號： | MCM72F7ADG9 |
| 廠商： | MOTOROLA INC |
| 元件分類： | DRAM |
| 英文描述： | 512KB and 1MB Synchronous Fast Static RAM Module |
| 中文描述： | 128K X 72 MULTI DEVICE SRAM MODULE, 9 ns, DMA168 |
| 封裝： | DIMM-168 |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 160K |
| 代理商： | MCM72F7ADG9 |
MCM72F6A
MCM72F7A
5
MOTOROLA FAST SRAM
PIN DESCRIPTIONS
Pin Locations
Symbol
Type
Description
72, 155, 71, 154, 70, 152,
68, 151, 67, 149, 65, 148,
64, 146, 62, 145
A0 – A15
Input
Synchronous Address Inputs: These inputs are registered and must meet
setup and hold times.
156
ADSP
Input
Synchronous Addresss Status Controller: Initiates read, write, or chip
deselect cycle.
134, 44, 121, 31,
105, 15, 92, 86
DP0 – DP7
Synchronous Parity Data Inputs/Outputs.
140, 56, 139, 55, 137, 53,
136, 52, 50, 133, 49, 131,
47, 130, 46, 128, 127, 43,
125, 41, 124, 40, 122, 38,
37, 119, 35, 118, 34, 116,
32, 115, 111, 27, 110, 26,
108, 24, 107, 23, 21, 104,
20, 102, 18, 101, 17, 99,
98, 14, 96, 12, 95, 11, 93,
9, 8, 90, 6, 89, 5, 87, 3, 2
DQ0 – DQ63
I/O
Synchronous Data Inputs/Outputs.
167, 83
E0, E1
Input
Synchronous Chip Enable: Active low to enable chip. Negated high —
deselects chip when ADSP is asserted. E1 is only used on 1MB module.
166, 82
G0, G1
Input
Asynchronous Output Enable Input:
Low — enables output buffer.
High — DQx pins are high impedance.
G1 is only used on 1MB module.
158, 74, 113, 29
K0 – K3
Input
Clock: This signal registers the address, data in, and all control signals
except G0 and G1.
164, 80, 163, 79, 161,
77, 160, 76
W0 – W7
Input
Synchronous Byte Write Inputs.
4, 16, 33, 45, 57, 69, 94,
106, 123, 135, 147, 165
VDD
Supply
Power Supply: 3.3 V + 10%, – 5%. Must be connected on all modules.
1, 7, 10, 13, 19, 22, 25, 28,
30, 36, 39, 42, 48, 51, 54, 60,
63, 66, 73, 75, 78, 81, 84, 85,
88, 91, 97, 100, 103, 109,
112, 114, 117, 120, 126, 129,
132, 138, 141, 144, 150, 153,
157, 159, 162, 168
VSS
Supply
Ground.
58, 59, 61, 142, 143
NC
No Connection: There is no connection to the chip.
DATA RAM MCM69F618A SYNCHRONOUS TRUTH TABLE
(See Notes 1, 2, 3, and 4)
Next Cycle
Address Used
Ex
ADSP
Gx
DQx
WRITE
Deselect
None
1
0
X
High–Z
X
Begin Read
External Address
0
0
0
DQ
Read
Read
Current
X
1
1
High–Z
Read
Read
Current
X
1
0
DQ
Read
Begin Write
External
0
0
X
High–Z
Write
Write
Current
X
1
X
High–Z
Write
NOTES:
1. X = don’t care, 1 = logic high, 0 = logic low.
2. Write is defined as any Wx low.
3. G is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (tGLQX) following G going low.
4. On write cycles that follow read cycles, G must be negated prior to the start of the write cycle to ensure proper write data setup times. G must
also remain negated at the completion of the write cycle to ensure proper write data hold times.
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