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參數(shù)資料
| 型號： | MCM8A10 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 1M x 8 Bit Fast Static RAM Module |
| 中文描述： | 100萬× 8位快速靜態(tài)存儲器模塊 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 79K |
| 代理商： | MCM8A10 |
MCM8A10
6
MOTOROLA FAST SRAM
WRITE CYCLE 1
(W Controlled, See Notes 1 and 2)
Parameter
Symbol
b l
MCM8A10–15
U i
Unit
Notes
Min
Max
Write Cycle Time
tAVAV
tAVWL
tAVWH
tWLWH,
tWLEH
15
—
ns
3
Address Setup Time
0
—
ns
Address Valid to End of Write
12
—
ns
Write Pulse Width
12
—
ns
Data Valid to End of Write
tDVWH
tWHDX
tWLQZ
tWHQX
tWHAX
7
—
ns
Data Hold TIme
0
—
ns
Write Low to Data High–Z
0
6
ns
4, 5, 6
Write High to Output Active
5
—
ns
4, 5, 6
Write Recovery Time
0
—
ns
NOTES:
1. A write occurs during the overlap of E low and W low.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. All timings are referenced from the last valid address to the first transitioning address.
4. Transition is measured
±
500 mV from steady–state voltage with load of Figure 1b.
5. This parameter is sampled and not 100% tested.
6. At any given voltage and temperature, tWLQZ max is less than tWHQX min both for a given device and from device to device.
tAVWH
tWLQZ
tWHAX
tDVWH
A (ADDRESS)
E (CHIP ENABLE)
W (WRITE ENABLE)
D (DATA IN)
Q (DATA OUT)
DATA VALID
HIGH–Z
HIGH–Z
tAVAV
tAVWL
tWLEH
tWLWH
tWHDX
tWHQX
WRITE CYCLE 1
(W Controlled See Notes 1 and 2)
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