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參數(shù)資料
| 型號： | MCP2200T-I/SS |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 2/34頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC USB 2.0 - UART 20SSOP |
| 標準包裝： | 1,600 |
| 特點： | USB 至 UART |
| 通道數(shù)： | 8 |
| FIFO's： | 256 字節(jié) |
| 規(guī)程： | USB 2.0 |
| 電源電壓： | 3 V ~ 5.5 V |
| 帶自動流量控制功能： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SSOP（0.209"，5.30mm 寬） |
| 供應商設備封裝： | 20-SSOP |
| 包裝： | 帶卷 (TR) |
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MCP2003/4/3A/4A
DS22230D-page 10
2010-2011 Microchip Technology Inc.
Fault condition or by an external drive. While the
transmitter is disabled, the internal 30 k
Ω pull-up
resistor on the LBUS pin is also disconnected to reduce
current.
TABLE 1-3:
FAULT/TXE TRUTH TABLE
1.5.5
TRANSMIT DATA INPUT (TXD)
The Transmit Data Input pin has an internal pull-up.
The LIN pin is low (dominant) when TXD is low, and high
(recessive) when TXD is high.
For extra bus security, TXD is internally forced to ‘1’
whenever the transmitter is disabled regardless of
external TXD voltage.
1.5.5.1
TXD Dominant Timeout
If TXD is driven low for longer than approximately 25
mS, the LBUS pin is switched to recessive mode and
the part enters TOFF Mode. This is to prevent the LIN
node from permanently driving the LIN Bus dominant.
The transmitter is reenabled on TXD rising edge.
1.5.6
GROUND (VSS)
This is the Ground pin.
1.5.7
LIN BUS (LBUS)
The bidirectional LIN Bus pin (LBUS) is controlled by the
TXD input. LBUS has a current limited open collector
output. To reduce EMI, the edges during the signal
changes are slope controlled and include corner
rounding control for both falling and rising edges.
The internal LIN receiver observes the activities on the
LIN bus, and matches the output signal RXD to follow
the state of the LBUS pin.
1.5.7.1
Bus Dominant Timer
The Bus Dominant Timer is an internal timer that
deactivates the LBUS transmitter after approximately
25 milliseconds of dominant state on the LBUS pin. The
timer is reset on any recessive LBUS state.
The LIN bus transmitter will be reenabled after a
recessive state on the LBUS pin as long as CS is high.
Disabling can be caused by the LIN bus being
externally held dominant, or by TXD being driven low.
Additionally, on the MCP2004/2004A, the FAULT pin
will be driven low to indicate the Transmitter Off state.
1.5.8
BATTERY (VBB)
This is the Battery Positive Supply Voltage pin.
1.5.9
VOLTAGE REGULATOR ENABLE
OUTPUT (VREN)
This is the External Voltage Regulator Enable pin.
Open source output is pulled high to VBB in all modes,
except Power-Down.
1.5.10
EXPOSED THERMAL PAD (EP)
Do not electrically connect, or connect to Vss.
Note:
The FAULT/TXE pin is true (‘0’) whenever
the internal circuits have detected a short
or thermal excursion and have disabled
the LBUS output driver.
TXD
In
RXD
Out
LINBUS
I/O
Thermal
Override
FAULT/TXE
Definition
External
Input
Driven
Output
LH
VBB
OFF
H
L
FAULT, TXD driven low, LINBUS shorted to VBB
HH
VBB
OFF
H
OK
L
GND
OFF
H
OK
H
L
GND
OFF
H
OK, data is being received from the LINBUS
xx
VBB
ON
H
L
FAULT, Transceiver in thermal shutdown
xx
VBB
x
L
x
NO FAULT, the CPU is commanding the
transceiver to turn off the transmitter driver
Legend: x = don’t care
Note 1:
The FAULT/TXE is valid after approximately 25 s after TXD falling edge. This is to eliminate false fault
reporting during bus propagation delays.
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