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| 型號： | MCP23016-I/SP |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 7/38頁 |
| 文件大小： | 0K |
| 描述： | IC I/O EXPANDER I2C 16B 28SDIP |
| 標(biāo)準(zhǔn)包裝： | 15 |
| 接口： | I²C |
| 輸入/輸出數(shù)： | 16 |
| 中斷輸出： | 是 |
| 頻率 - 時鐘： | 400kHz |
| 電源電壓： | 2 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 28-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 28-DIP |
| 包裝： | 管件 |
| 包括： | POR |
| 產(chǎn)品目錄頁面： | 684 (CN2011-ZH PDF) |
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2007 Microchip Technology Inc.
DS20090C-page 15
MCP23016
1.9.3
READING THE REGISTERS
To read a MCP23016 register, the Master needs to
follow the requirements shown in Figure 1-6. First, the
device is selected by sending the slave address and
setting the R/W bit to logic ‘0’. The command byte is
sent after the address and determines which register
will be read. A restart condition is generated and the
device address is sent again with the R/W bit set to
logic ‘1’. The data register defined by the command
byte will be sent first, followed by the other register in
the register pair. The logic for register selection is the
same as explained in Write mode (Section 1.9.2,
“Writing the Registers”).
The falling edge of the ninth clock initiates the register
read action. The SCL clock will be held low while the
data is read from the register and is transferred to the
I2C bus control block by the Serializer/Deserializer
block.
The MCP23016 holds the clock low after the falling
edge of the ninth clock pulse. The configuration
registers (or port control registers) are read and the
value is stored. Finally, the clock is released to enable
the next transmission.
There is no limitation on the number of data bytes in
one read transmission. Figure 1-8 shows the case of
multiple byte read in one read operation. In this case,
the multiple writes are made to the same data pair.
FIGURE 1-6:
READ FROM
CONFIGURATION
REGISTER
Note:
The bus must remain free until after the
ninth clock pulse for a minimum of 12 s
(see Table 2-5 and Figure 2-4).
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
0
A2
A1
A0
D0
S
0
R/
W
=0
AC
K
D6
D5
D4
D3
D2
D1
D7
AC
K
A
ddres
s
Com
m
a
nd
B
y
te
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
0
A2
A1
A0
D0
S
0
R/
W
=0
AC
K
D6
D5
D4
D3
D2
D1
D7
AC
K
Addr
ess
Dat
a
f
rom
LSB
or
MSB
of
regist
er
1
2
3
4
5
6
7
8
9
D0
D6
D5
D4
D3
D2
D1
D7
AC
K
Da
ta
fr
om
M
S
B
or
LS
B
of
regist
er
P
SD
A
SC
L
S
C
L
hel
d
l
o
w
u
n
ti
l
da
ta
i
s
pr
oc
e
s
e
d
SCL
h
e
ld
lo
w
u
n
til
da
ta
i
s
pr
oce
ssed
0
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