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| 型號： | MCP2515-I/P |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 56/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CAN CONTROLLER W/SPI 18DIP |
| 產(chǎn)品培訓模塊： | CAN Bus Protection |
| 標準包裝： | 25 |
| 控制器類型： | CAN 接口 |
| 接口： | SPI 串行 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 電流 - 電源： | 10mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 18-DIP（0.300"，7.62mm） |
| 供應商設備封裝： | 18-PDIP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 685 (CN2011-ZH PDF) |
| 配用： | MCP2515DM-BM-ND - BOARD DEMO FOR MCP2515/51 MCP2515DM-PTPLS-ND - BOARD DAUGHTER PICTAIL MCP2515 MCP2515DM-PCTL-ND - BOARD DEMO FOR MCP2515 DV251001-ND - KIT DEVELOPMENT CAN MCP2510 |
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MCP2515
DS21801F-page 6
2010 Microchip Technology Inc.
1.5
CAN Protocol Engine
The CAN protocol engine combines several functional
blocks, shown in Figure 1-4 and described below.
1.5.1
PROTOCOL FINITE STATE
MACHINE
The heart of the engine is the Finite State Machine
(FSM). The FSM is a sequencer that controls the
sequential data stream between the TX/RX shift
register, the CRC register and the bus line. The FSM
also controls the Error Management Logic (EML) and
the parallel data stream between the TX/RX shift
registers and the buffers. The FSM ensures that the
processes of reception, arbitration, transmission and
error-signaling are performed according to the CAN
protocol. The automatic retransmission of messages
on the bus line is also handled by the FSM.
1.5.2
CYCLIC REDUNDANCY CHECK
The Cyclic Redundancy Check register generates the
Cyclic Redundancy Check (CRC) code, which is
transmitted after either the Control Field (for messages
with 0 data bytes) or the Data Field and is used to
check the CRC field of incoming messages.
1.5.3
ERROR MANAGEMENT LOGIC
The Error Management Logic (EML) is responsible for
the fault confinement of the CAN device. Its two
counters, the Receive Error Counter (REC) and the
Transmit Error Counter (TEC), are incremented and
decremented by commands from the bit stream
processor. Based on the values of the error counters,
the CAN controller is set into the states error-active,
error-passive or bus-off.
1.5.4
BIT TIMING LOGIC
The Bit Timing Logic (BTL) monitors the bus line input
and handles the bus-related bit timing according to the
CAN protocol. The BTL synchronizes on a recessive-
to-dominant bus transition at Start-of-Frame (hard
synchronization) and on any further recessive-to-
dominant bus line transition if the CAN controller itself
does not transmit a dominant bit (resynchronization).
The BTL also provides programmable time segments
to compensate for the propagation delay time, phase
shifts and to define the position of the sample point
within the bit time. The programming of the BTL
depends on the baud rate and external physical delay
times.
FIGURE 1-4:
CAN PROTOCOL ENGINE BLOCK DIAGRAM
Bit Timing Logic
CRC<14:0>
Comparator
Receive<7:0>
Transmit<7:0>
Sample<2:0>
Majority
Decision
StuffReg<5:0>
Comparator
Transmit Logic
Receive
Error Counter
Transmit
Error Counter
Protocol
FSM
RX
SAM
BusMon
Rec/Trm Addr.
RecData<7:0>
TrmData<7:0>
Shift<14:0>
(Transmit<5:0>, Receive<7:0>)
TX
REC
TEC
ErrPas
BusOff
Interface to Standard Buffer
SOF
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MCP2515T | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:Stand-Alone CAN Controller with SPI Interface |
| MCP2515T-E/ML | 功能描述:網(wǎng)絡控制器與處理器 IC CAN controller with SPI interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| MCP2515T-E/SO | 功能描述:網(wǎng)絡控制器與處理器 IC W/ SPI Inter 125dC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| MCP2515T-E/ST | 功能描述:網(wǎng)絡控制器與處理器 IC W/ SPI Inter 125dC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| MCP2515T-I/M | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:Stand-Alone CAN Controller with SPI Interface |
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