參數(shù)資料
型號： mcp3208
廠商： Microchip Technology Inc.
元件分類： 串行ADC
英文描述： 2.7V 4-Channel/8-Channel 12-Bit A/D Converters With SPI Serial Interface(SPI串行接口的8通道12位A/D轉(zhuǎn)換器)
中文描述： 2.7 4-Channel/8-Channel 12位A / D轉(zhuǎn)換器具有SPI串行接口（SPI串行接口的8通道12位的A / D轉(zhuǎn)換器）
文件頁數(shù)： 3/34頁
文件大小： 673K
代理商： MCP3208
2002 Microchip Technology Inc.
DS21298C-page 3
MCP3204/3208
Analog Inputs
Input Voltage Range for CH0-
CH7 in Single-Ended Mode
Input Voltage Range for IN+ in
pseudo-differential Mode
Input Voltage Range for IN- in
pseudo-differential Mode
Leakage Current
Switch Resistance
Sample Capacitor
Digital Input/Output
Data Coding Format
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Output Leakage Current
Pin Capacitance
(All Inputs/Outputs)
Timing Parameters
Clock Frequency
V
SS
—
V
REF
V
IN-
—
V
REF
+IN-
V
SS
-100
—
V
SS
+100
mV
—
—
—
0.001
1000
20
±1
—
—
μA
pF
See Figure 4-1
See Figure 4-1
Straight Binary
0.7 V
DD
—
4.1
—
-10
-10
—
V
IH
V
IL
V
OH
V
OL
I
LI
I
LO
—
—
—
—
—
—
—
—
V
V
V
V
μA
μA
pF
0.3 V
DD
—
0.4
10
10
10
I
OH
= -1 mA, V
DD
= 4.5V
I
OL
= 1 mA, V
DD
= 4.5V
V
IN
= V
SS
or V
DD
V
OUT
= V
SS
or V
DD
V
DD
= 5.0V (
Note 1
)
T
AMB
= 25°C, f = 1 MHz
C
IN
,C
OUT
f
CLK
—
—
250
250
100
—
—
—
—
—
2.0
1.0
—
—
—
MHz
MHz
ns
ns
ns
V
DD
= 5V (
Note 3
)
V
DD
= 2.7V (
Note 3
)
Clock High Time
Clock Low Time
CS Fall To First Rising CLK
Edge
Data Input Setup Time
Data Input Hold Time
CLK Fall To Output Data Valid
CLK Fall To Output Enable
CS Rise To Output Disable
CS Disable Time
D
OUT
Rise Time
D
OUT
Fall Time
Power Requirements
Operating Voltage
Operating Current
t
HI
t
LO
t
SUCS
t
SU
t
HD
t
DO
t
EN
t
DIS
t
CSH
t
R
t
F
—
—
—
—
—
500
—
—
—
—
—
—
—
—
—
—
50
50
200
200
100
—
100
100
ns
ns
ns
ns
ns
ns
ns
ns
See Figures 1-2 and 1-3
See Figures 1-2 and 1-3
See Figures 1-2 and 1-3
See Figures 1-2 and 1-3 (
Note 1
)
See Figures 1-2 and 1-3 (
Note 1
)
V
DD
I
DD
2.7
—
—
—
—
320
225
0.5
5.5
400
—
2.0
V
μA
V
DD
=V
REF
= 5V, D
OUT
unloaded
V
DD
=V
REF
= 2.7V, D
OUT
unloaded
CS = V
DD
= 5.0V
Standby Current
Note 1:
This parameter is established by characterization and not 100% tested.
2:
See graphs that relate linearity performance to V
REF
levels.
3:
Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity
performance, particularly at elevated temperatures. See Section 6.2, “Maintaining Minimum Clock Speed”,
for more information.
I
DDS
μA
ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics:
Unless otherwise noted, all parameters apply at V
DD
= 5V, V
SS
= 0V, V
REF
= 5V,
T
AMB
= -40°C to +85°C,f
SAMPLE
= 100 ksps and f
CLK
= 20*f
SAMPLE
Parameters
Sym
Min
Typ
Max
Units
Conditions
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