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參數(shù)資料
| 型號： | MCP3422A0T-E/MC |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 4/58頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 18BIT 3.75SPS 2CH 8-DFN |
| 產(chǎn)品培訓(xùn)模塊： | MCP3901 Analog Front End |
| 標準包裝： | 3,300 |
| 位數(shù)： | 18 |
| 采樣率（每秒）： | 3.75 |
| 數(shù)據(jù)接口： | I²C，串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-VFDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 8-DFN（2x3） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個單端，雙極；2 個差分，雙極 |
| 配用： | MCP3422EV-ND - BOARD EVAL MCP3422 PICKIT SERIAL |
| 其它名稱： | MCP3422A0T-E/MCTR |
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MCP3422/3/4
DS22088C-page 12
2009 Microchip Technology Inc.
FIGURE 3-1:
Equivalent Analog Input Circuit.
3.3
Serial Clock Pin (SCL)
SCL is the serial clock pin of the I2C interface. The
device act only as a slave and the SCL pin accepts
only external serial clocks. The input data from the
Master device is shifted into the SDA pin on the rising
edges of the SCL clock and output from the slave
device occurs at the falling edges of the SCL clock.
The SCL pin is an open-drain N-channel driver.
Therefore, it needs a pull-up resistor from the VDD line
to the SCL pin. Refer to Section 5.3 “I2C Serial Com-
communication.
3.4
Serial Data Pin (SDA)
SDA is the serial data pin of the I2C interface. The SDA
pin is used for input and output data. In read mode, the
conversion result is read from the SDA pin (output). In
write mode, the device configuration bits are written
(input) though the SDA pin. The SDA pin is an open-
drain N-channel driver. Therefore, it needs a pull-up
resistor from the VDD line to the SDA pin. Except for
start and stop conditions, the data on the SDA pin must
be stable during the high period of the clock. The high
or low state of the SDA pin can only change when the
clock signal on the SCL pin is low. Refer to Section 5.3
Serial Interface communication.
Typical range of the pull-up resistor value for SCL and
SDA is from 5 k
Ω to 10 kΩ for standard (100 kHz) and
fast (400 kHz) modes, and less than 1 k
Ω for high
speed mode (3.4 MHz).
3.5
Exposed Thermal Pad (EP)
There is an internal electrical connection between the
Exposed Thermal Pad (EP) and the VSS pin; they must
be connected to the same potential on the Printed
Circuit Board (PCB).
CPIN
V
RSS CHn
4pF
VT = 0.6V
ILEAKAGE
Sampling
Switch
SS
RS
CSAMPLE
(3.2 pF)
VDD
(~ ±1 nA)
LEGEND
V
=
Signal Source
ILEAKEAGE
=
Leakage Current at Analog Pin
RSS
=
Source Impedance
SS
=
Sampling Switch
CHn
=
Analog Input Pin
RS
=
Sampling Switch Resistor
CPIN
=
Input Pin Capacitance
CSAMPLE
=
Sample Capacitance
VT
=
Threshold Voltage
D1, D2 =
ESD Protection Diode
D1
D2
VSS
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