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參數(shù)資料
| 型號： | MCP4132-502E/SN |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 21/59頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RHEO DGTL SNGL 5K SPI 8SOIC |
| 標(biāo)準(zhǔn)包裝： | 100 |
| 接片： | 129 |
| 電阻（歐姆）： | 5k |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 150 ppm/°C |
| 存儲器類型： | 易失 |
| 接口： | 4 線 SPI（芯片選擇） |
| 電源電壓： | 1.8 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOICN |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 675 (CN2011-ZH PDF) |
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Micrel, Inc.
KSZ8051MNL/RNL
July 2010
28
M9999-070910-1.0
RMII Back-to-Back Mode (KSZ8051RNL only)
In RMII Back-to-Back mode, a KSZ8051RNL interfaces with another KSZ8051RNL, or a KSZ8041FTL to provide a
complete 100Mbps copper repeater, or media converter solution, respectively.
The KSZ8051RNL devices are configured to RMII Back-to-Back mode after power-up or reset with the following:
Strapping pin CONFIG[2:0] (pins 18, 29, 28) set to ‘101’
A common 50MHz reference clock connected to XI (pin 9)
RMII signals connected as shown in the following table.
KSZ8051RNL (100Base-TX copper)
[Device 1]
KSZ8051RNL (100Base-TX copper)
[Device 2]
Pin Name
Pin Number
Pin Type
Pin Name
Pin Number
Pin Type
CRSDV
18
Output
TXEN
23
Input
RXD1
15
Output
TXD1
25
Input
RXD0
16
Output
TXD0
24
Input
TXEN
23
Input
CRSDV
18
Output
TXD1
25
Input
RXD1
15
Output
TXD0
24
Input
RXD0
16
Output
Table 4. RMII Signal Connection for RMII Back-to-Back Mode (100Base-TX Copper Repeater)
MII Management (MIIM) Interface
The KSZ8051MNL/RNL supports the IEEE 802.3 MII Management Interface, also known as the Management Data Input /
Output (MDIO) Interface. This interface enables upper-layer device, like a MAC processor, to monitor and control the state
of the KSZ8051MNL/RNL. An external device with MIIM capability is used to read the PHY status and/or configure the
PHY settings. Further details on the MIIM interface can be found in Clause 22.2.4 of the IEEE 802.3 Specification.
The MIIM interface consists of the following:
A physical connection that incorporates the clock line (MDC) and the data line (MDIO).
A specific protocol that operates across the aforementioned physical connection that allows the external controller
to communicate with one or more PHY devices.
A set of 16-bit MDIO registers. Registers [0:8] are standard registers, and their functions are defined per the IEEE
802.3 Specification. The additional registers are provided for expanded functionality. See “Register Map” section
for details.
As the default, the KSZ8051MNL/RNL supports unique PHY addresses 1 to 7, and broadcast PHY address 0. The latter is
defined per the IEEE 802.3 Specification, and can be used to read/write to a single KSZ8051MNL/RNL device, or write to
multiple KSZ8051MNL/RNL devices simultaneously.
Optionally, PHY address 0 can be disabled as the broadcast address by either hardware pin strapping (B-CAST_OFF, pin
19) or software (register 16h, bit 9), and assigned as a unique PHY address.
The PHYAD[2:0] strapping pins are used to assigned a unique PHY address between 0 and 7 to each KSZ8051MNL/RNL
device.
The following table shows the MII Management frame format for the KSZ8051MNL/RNL.
Preamble
Start of
Frame
Read/Write
OP Code
PHY
Address
Bits [4:0]
REG
Address
Bits [4:0]
TA
Data
Bits [15:0]
Idle
Read
32 1’s
01
10
00AAA
RRRRR
Z0
DDDDDDDD_DDDDDDDD
Z
Write
32 1’s
01
00AAA
RRRRR
10
DDDDDDDD_DDDDDDDD
Z
Table 5. MII Management Frame Format – for KSZ8051MNL/RNL
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