SPI REQUIREMENTS FOR SDI/SDO MULTIPLEXED (READ OPER" />
參數(shù)資料
型號: MCP4132-502E/SN
廠商: Microchip Technology
文件頁數(shù): 5/59頁
文件大?。?/td> 0K
描述: IC RHEO DGTL SNGL 5K SPI 8SOIC
標(biāo)準(zhǔn)包裝: 100
接片: 129
電阻(歐姆): 5k
電路數(shù): 1
溫度系數(shù): 標(biāo)準(zhǔn)值 150 ppm/°C
存儲器類型: 易失
接口: 4 線 SPI(芯片選擇)
電源電壓: 1.8 V ~ 5.5 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOICN
包裝: 管件
產(chǎn)品目錄頁面: 675 (CN2011-ZH PDF)
2008 Microchip Technology Inc.
DS22060B-page 13
MCP413X/415X/423X/425X
TABLE 1-3:
SPI REQUIREMENTS FOR SDI/SDO MULTIPLEXED (READ OPERATION ONLY) (2)
Characteristic
Symbol
Min
Max Units
Conditions
SCK Input Frequency
FSCK
—250
kHz
VDD = 2.7V to 5.5V
CS Active (VIL or VIHH) to SCK↑ input
TcsA2scH
60
ns
SCK input high time
TscH
1.8
us
SCK input low time
TscL
1.8
ns
Setup time of SDI input to SCK
↑ edge
TDIV2scH
40
ns
Hold time of SDI input from SCK
↑ edge
TscH2DIL40
ns
CS Inactive (VIH) to SDO output hi-impedance
TcsH2DOZ
50
ns
SDO data output valid after SCK
↓ edge
TscL2DOV—
1.6
us
SDO data output valid after
CS Active (VIL or VIHH)
TssL2doV
50
ns
CS Inactive (VIH) after SCK↓ edge
TscH2csI
100
ns
Hold time of CS Inactive (VIH) to
CS Active (VIL or VIHH)
TcsA2csI
50
ns
Note 1: This specification by design.
2: This table is for the devices where the SPI’s SDI and SDO pins are multiplexed (SDI/SDO) and a Read
command is issued. This is NOT required for SDI/SDO operation with the Increment, Decrement, or Write
commands. This data rate can be increased by having external pull-up resistors to increase the rising
edges of each bit.
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