參數(shù)資料
型號(hào)： MCP4161-104E/P
廠商： Microchip Technology
文件頁數(shù)： 20/88頁
文件大?。?/td> 0K
描述： IC POT DGTL SNGL 100K SPI 8DIP
標(biāo)準(zhǔn)包裝： 60
系列： WiperLock™
接片： 257
電阻（歐姆）： 100k
電路數(shù)： 1
溫度系數(shù)： 標(biāo)準(zhǔn)值 150 ppm/°C
存儲(chǔ)器類型： 易失
接口： 3 線 SPI（芯片選擇）
電源電壓： 1.8 V ~ 5.5 V
工作溫度： -40°C ~ 125°C
安裝類型： 通孔
封裝/外殼： 8-DIP（0.300"，7.62mm）
供應(yīng)商設(shè)備封裝： 8-PDIP
包裝： 管件
產(chǎn)品目錄頁面： 675 (CN2011-ZH PDF)
2008 Microchip Technology Inc.
DS22059B-page 27
MCP414X/416X/424X/426X
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
Additional descriptions of the device pins follows.
TABLE 3-1:
PINOUT DESCRIPTION FOR THE MCP414X/416X/424X/426X
Pin
Weak
Pull-up/
down
Standard Function
Single
Dual
Symbol
I/O
Buffer
Type
Rheo Pot (1) Rheo
Pot
8L
10L
14L
16L
1
111
16
CS
I
HV w/ST
“smart” SPI Chip Select Input
2
1
SCK
I
HV w/ST
“smart” SPI Clock Input
3
—
3
2
SDI
I
HV w/ST
“smart” SPI Serial Data Input
—
3
—
SDI/SDO
I/O
HV w/ST
“smart” SPI Serial Data Input/Output
4
444
3, 4
VSS
—P
—
Ground
—
5
P1B
A
Analog
No
Potentiometer 1 Terminal B
—
6
P1W
A
Analog
No
Potentiometer 1 Wiper Terminal
—
7
P1A
A
Analog
No
Potentiometer 1 Terminal A
—
5
—
8
P0A
A
Analog
No
Potentiometer 0 Terminal A
5
6
7
9
P0W
A
Analog
No
Potentiometer 0 Wiper Terminal
6
7
8
10
P0B
A
Analog
No
Potentiometer 0 Terminal B
——
—
11
12
WP
I
“smart” Hardware
EEPROM
Write
Protect
—
12
13
SHDN
I
HV w/ST
“smart” Hardware Shutdown
7
—
9
13
14
SDO
O
No
SPI Serial Data Out
8
10
14
15
VDD
—P
—
Positive Power Supply Input
—
———
11
NC
—
No Connection
99
11
—
17
EP
—
Exposed Pad. (Note 4)
Legend:
HV w/ST = High Voltage tolerant input (with Schmidtt trigger input)
A = Analog pins (Potentiometer terminals)
I = digital input (high Z)
O = digital output
I/O = Input / Output
P = Power
Note 1:
The 8-lead Single Potentiometer devices are pin limited so the SDO pin is multiplexed with the SDI pin
(SDI/SDO pin). After the Address/Command (first 6-bits) are received, If a valid Read command has been
requested, the SDO pin starts driving the requested read data onto the SDI/SDO pin.
2:
The pin’s “smart” pull-up shuts off while the pin is forced low. This is done to reduce the standby and shut-
down current.
3:
The SDO is an open drain output, which uses the internal “smart” pull-up. The SDI input data rate can be
at the maximum SPI frequency. the SDO output data rate will be limited by the “speed” of the pull-up,
customers can increase the rate with external pull-up resistors.
4:
The DFN and QFN packages have a contact on the bottom of the package. This contact is conductively
connected to the die substrate, and therefore should be unconnected or connected to the same ground as
the device’s VSS pin.
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