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| 型號： | MCP4241T-103E/SL |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 42/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DGTL POT 10K 2CH 14SOIC |
| 標(biāo)準(zhǔn)包裝： | 2,600 |
| 系列： | WiperLock™ |
| 接片： | 129 |
| 電阻（歐姆）： | 10k |
| 電路數(shù)： | 2 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 150 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | 4 線 SPI（芯片選擇） |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-SOIC |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | MCP4241T-103E/SLTR |
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2008 Microchip Technology Inc.
DS22059B-page 47
MCP414X/416X/424X/426X
7.2
Data Byte
Only the Read Command and the Write Command use
the Data Byte, see Figure 7-1. These commands
concatenate the 8-bits of the Data Byte with the one
data bit (D8) contained in the Command Byte to form
9-bits of data (D8:D0). The Command Byte format
supports up to 9-bits of data so that the 8-bit resistor
network can be set to Full Scale (100h or greater). This
allows wiper connections to Terminal A and to
Terminal B.
The D9 bit is currently unused, and corresponds to the
position on the SDO data of the CMDERR bit.
7.3
Error Condition
The CMDERR bit indicates if the four address bits
received (AD3:AD0) and the two command bits
received (C1:C0) are a valid combination (see
Table 4-1). The CMDERR bit is high if the combination
is valid and low if the combination is invalid.
The command error bit will also be low if a write to a
Non-Volatile Address has been specified and another
SPI command occurs before the CS pin is driven
inactive (VIH).
SPI commands that do not have a multiple of 8 clocks
are ignored.
Once an error condition has occurred, any following
commands are ignored. All following SDO bits will be
low until the CMDERR condition is cleared by forcing
the CS pin to the inactive state (VIH).
7.3.1
ABORTING A TRANSMISSION
All SPI transmissions must have the correct number of
SCK pulses to be executed. The command is not
executed until the complete number of clocks have
been received. Some commands also require the CS
pin to be forced inactive (VIH). If the CS pin is forced to
the inactive state (VIH) the serial interface is reset.
Partial commands are not executed.
SPI is more susceptible to noise than other bus
protocols. The most likely case is that this noise
corrupts the value of the data being clocked into the
MCP4XXX or the SCK pin is injected with extra clock
pulses. This may cause data to be corrupted in the
device, or a command error to occur, since the address
and command bits were not a valid combination. The
extra SCK pulse will also cause the SPI data (SDI) and
clock (SCK) to be out of sync. Forcing the CS pin to the
inactive state (VIH) resets the serial interface. The SPI
interface will ignore activity on the SDI and SCK pins
until the CS pin transition to the active state is detected
(VIH to VIL or VIH to VIHH).
Note 1:
When data is not being received by the
MCP4XXX, It is recommended that the
CS pin be forced to the inactive level (VIL)
2:
It is also recommended that long continu-
ous command strings should be broken
down into single commands or shorter
continuous
command
strings.
This
reduces the probability of noise on the
SCK pin corrupting the desired SPI
commands.
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