參數(shù)資料
型號： MCP4241T-103E/SL
廠商： Microchip Technology
文件頁數(shù)： 58/88頁
文件大?。?/td> 0K
描述： IC DGTL POT 10K 2CH 14SOIC
標準包裝： 2,600
系列： WiperLock™
接片： 129
電阻（歐姆）： 10k
電路數(shù)： 2
溫度系數(shù)： 標準值 150 ppm/°C
存儲器類型： 非易失
接口： 4 線 SPI（芯片選擇）
電源電壓： 2.7 V ~ 5.5 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 14-SOIC（0.154"，3.90mm 寬）
供應商設備封裝： 14-SOIC
包裝： 帶卷 (TR)
其它名稱： MCP4241T-103E/SLTR
2008 Microchip Technology Inc.
DS22059B-page 61
MCP414X/416X/424X/426X
8.4
Design Considerations
In the design of a system with the MCP4XXX devices,
the following considerations should be taken into
account:
8.4.1
POWER SUPPLY
CONSIDERATIONS
The typical application will require a bypass capacitor
in order to filter high-frequency noise, which can be
induced onto the power supply's traces. The bypass
capacitor helps to minimize the effect of these noise
sources on signal integrity. Figure 8-6 illustrates an
appropriate bypass strategy.
In this example, the recommended bypass capacitor
value is 0.1 F. This capacitor should be placed as
close (within 4 mm) to the device power pin (VDD) as
possible.
The power source supplying these devices should be
as clean as possible. If the application circuit has
separate digital and analog power supplies, VDD and
VSS should reside on the analog plane.
FIGURE 8-6:
Typical Microcontroller
Connections.
8.4.2
LAYOUT CONSIDERATIONS
Inductively-coupled AC transients and digital switching
noise can degrade the input and output signal integrity,
potentially masking the MCP4XXX’s performance.
Careful board layout minimizes these effects and
increases the Signal-to-Noise Ratio (SNR). Multi-layer
boards utilizing a low-inductance ground plane,
isolated inputs, isolated outputs and proper decoupling
are critical to achieving the performance that the silicon
is capable of providing. Particularly harsh environ-
ments may require shielding of critical signals.
If low noise is desired, breadboards and wire-wrapped
boards are not recommended.
8.4.3
RESISTOR TEMPCO
Characterization curves of the resistor temperature
coefficient (Tempco) are shown in Figure 2-8,
These curves show that the resistor network is
designed to correct for the change in resistance as
temperature increases. This technique reduces the
end to end change is RAB resistance.
8.4.4
HIGH VOLTAGE TOLERANT PINS
High Voltage support (VIHH) on the Serial Interface pins
supports two features. These are:
In-Circuit Accommodation of split rail applications
and power supply sync issues
User configuration of the Non-Volatile EEPROM,
Write Protect, and WiperLock feature
VDD
VSS
MCP414X/416X/
4
2
4
X/
42
6X
0.1 F
PIC
Mic
roc
on
trol
le
r
0.1 F
U/D
CS
W
B
A
Note:
In many applications, the High Voltage will
only be present at the manufacturing
stage so as to “l(fā)ock” the Non-Volatile wiper
value (after calibration) and the contents
of the EEPROM. This ensures that the
since High Voltage is not present under
normal operating conditions, that these
values can not be modified.
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