102A(5) T
參數(shù)資料
型號(hào)： MCP4716A0T-E/CH
廠商： Microchip Technology
文件頁(yè)數(shù)： 2/86頁(yè)
文件大?。?/td> 0K
描述： IC DAC 10BIT NV EEP I2C SOT-23-6
標(biāo)準(zhǔn)包裝： 1
設(shè)置時(shí)間： 6µs
位數(shù)： 10
數(shù)據(jù)接口： EEPROM，I²C，串行
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 單電源
功率耗散（最大）： 452mW
工作溫度： -40°C ~ 125°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： SOT-23-6
供應(yīng)商設(shè)備封裝： SOT-23-6
包裝： 標(biāo)準(zhǔn)包裝
輸出數(shù)目和類(lèi)型： 1 電壓，單極
采樣率（每秒）： *
其它名稱： MCP4716A0T-E/CHDKR
MCP4706/4716/4726
DS22272C-page 10
2011-2012 Microchip Technology Inc.
102A(5)
TRSCL
SCL rise time
100 kHz mode
—
1000
ns
Cb is specified to be from
10 to 400 pF (100 pF
maximum for 3.4 MHz
mode)
400 kHz mode
20 + 0.1Cb
300
ns
1.7 MHz mode
20
80
ns
1.7 MHz mode
20
160
ns
After a Repeated Start
condition or an
Acknowledge bit
3.4 MHz mode
10
40
ns
3.4 MHz mode
10
80
ns
After a Repeated Start
condition or an
Acknowledge bit
102B(5)
TRSDA
SDA rise time
100 kHz mode
—
1000
ns
Cb is specified to be from
10 to 400 pF (100 pF max
for 3.4 MHz mode)
400 kHz mode
20 + 0.1Cb
300
ns
1.7 MHz mode
20
160
ns
3.4 MHz mode
10
80
ns
103A(5)
TFSCL
SCL fall time
100 kHz mode
—
300
ns
Cb is specified to be from
10 to 400 pF (100 pF max
for 3.4 MHz mode)
400 kHz mode
20 + 0.1Cb
300
ns
1.7 MHz mode
20
80
ns
3.4 MHz mode
10
40
ns
103B(5)
TFSDA
SDA fall time
100 kHz mode
—
300
ns
Cb is specified to be from
10 to 400 pF (100 pF max
for 3.4 MHz mode)
400 kHz mode
20 + 0.1Cb(4)
300
ns
1.7 MHz mode
20
160
ns
3.4 MHz mode
10
80
ns
TABLE 1-3:
I2C BUS DATA REQUIREMENTS (SLAVE MODE) (CONTINUED)
I2C AC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
-40
°C ≤ TA ≤ +125°C (Extended)
Operating Voltage VDD range is described in Electrical Characteristics
Param.
No.
Sym
Characteristic
Min
Max
Units
Conditions
Note 1:
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
2:
A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but
the requirement tSU;DAT ≥ 250 ns must then be met. This will automatically be the case if the device does
not stretch the Low period of the SCL signal. If such a device does stretch the Low period of the SCL
signal, it must output the next data bit to the SDA line.
TR max.+tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard mode I
2C bus specification) before
the SCL line is released.
3:
The MCP47X6 device must provide a data hold time to bridge the undefined part between VIH and VIL of
the falling edge of the SCL signal. This specification is not a part of the I2C specification, but must be tested
in order to ensure that the output data will meet the setup and hold specifications for the receiving device.
4:
Use Cb in pF for the calculations.
5:
Not Tested. This parameter ensured by characterization.
6:
A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do
not unintentionally create a Start or Stop condition.
If this parameter is too short, it can create an unintentional Start or Stop condition to other devices on the
I2C bus line. If this parameter is too long, the Data Input Setup (TSU:DAT) or Clock Low time (TLOW) can be
affected.
Data Input: This parameter must be longer than tSP.
Data Output: This parameter is characterized, and tested indirectly by testing TAA parameter.
7:
Ensured by the TAA 3.4 MHz specification test.
8:
The specification is not part of the I
2
C specification. TAA = THD:DAT + TFSDA (or TRSDA).
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