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參數(shù)資料
| 型號： | MCP4716A0T-E/CH |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 37/86頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 10BIT NV EEP I2C SOT-23-6 |
| 標準包裝： | 1 |
| 設(shè)置時間： | 6µs |
| 位數(shù)： | 10 |
| 數(shù)據(jù)接口： | EEPROM，I²C，串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 452mW |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-6 |
| 供應(yīng)商設(shè)備封裝： | SOT-23-6 |
| 包裝： | 標準包裝 |
| 輸出數(shù)目和類型： | 1 電壓，單極 |
| 采樣率（每秒）： | * |
| 其它名稱： | MCP4716A0T-E/CHDKR |
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MCP4706/4716/4726
DS22272C-page 42
2011-2012 Microchip Technology Inc.
TABLE 4-3:
STATUS BITS OPERATION
Name
Function
RDY/BSY
This bit indicates the state of the EEPROM program memory
1
= EEPROM is not in a programming cycle
0
= EEPROM is in a programming cycle
POR
Power-on Reset Status Indicator (flag)
1
= Device is powered on with VDD > VPOR.
Ensure that VDD is above VDD(MIN) to ensure proper operation.
0
= Device is in powered off state. If this value is read, VDD < VDD(MIN) < VPOR.
Unreliable device operation should be expected.
TABLE 4-4:
CONFIGURATION BITS
Name
Function
VREF1:VREF0
Resistor Ladder Voltage Reference (VRL) Selection bits
0x
=VDD (Unbuffered)
10
=VREF pin (Unbuffered)
11
=VREF pin (Buffered)
PD1:PD0
Power-Down Selection bits
When the DAC is powered down, most of the internal circuits are powered off and the op amp is
disconnected from the VOUT pin.
00
= Not Powered Down (Normal operation)
01
= Powered Down – VOUT is loaded with 1 kΩ resistor to ground.
10
= Powered Down – VOUT is loaded with 100 kΩ resistor to ground.
11
= Powered Down – VOUT is loaded with 500 kΩ resistor to ground.
Note:
See Table 4-2 and Figure 4-7 for more details.
G
Gain Selection bit
0
=
1x (gain of 1)
1
=
2x (gain of 2). Not applicable when VDD is used as VRL
Note:
If VREF = VDD, the device uses a gain of 1 only, regardless of the gain selection bit (G)
setting.
TABLE 4-5:
CONFIGURATION BIT VALUES AFTER POR/BOR EVENT
R/W
Comment
Bit Name
VREF1
VREF0
PD1
PD0
G
POR Event
0(1)
When VDD transitions from VDD < VPOR to VDD > VPOR
BOR Event
001
10
When VDD transitions from VDD > VBOR to VDD < VBOR
Note 1:
Default configuration when the device is shipped to customer. The POR/BOR value may be modified by
writing the corresponding nonvolatile Configuration bit.
REGISTER 4-1:
DAC REGISTER BITS
R/W
Comment
Bit Name
—(2)
—(2)
D7
D6
D5
D4
D3
D2
D1
D0
MCP4706
—(2)
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
MCP4716
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
MCP4726
POR/BOR Event
0(1)
0(1)
0(1)
Note 1:
Default configuration when the device is shipped to customer. The POR/BOR value may be modified by
writing the corresponding nonvolatile Configuration bit.
2:
This device does not implement this bit, so there is no corresponding POR/BOR value.
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