參數(shù)資料
型號(hào)： MCP4725A1T-E/CH
廠商： Microchip Technology
文件頁(yè)數(shù)： 28/50頁(yè)
文件大?。?/td> 0K
描述： IC DAC 12BIT EE W/I2C SOT23-6
標(biāo)準(zhǔn)包裝： 1
設(shè)置時(shí)間： 6µs
位數(shù)： 12
數(shù)據(jù)接口： EEPROM，I²C，串行
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 單電源
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： SOT-23-6
供應(yīng)商設(shè)備封裝： SOT-23-6
包裝： 標(biāo)準(zhǔn)包裝
輸出數(shù)目和類型： 1 電壓，單極；1 電壓，雙極
采樣率（每秒）： *
產(chǎn)品目錄頁(yè)面： 673 (CN2011-ZH PDF)
配用： MCP4725DM-PTPLS-ND - BOARD DAUGHTER PICTAIL MCP4725
其它名稱： MCP4725A1T-E/CHDKR
MCP4725
DS22039D-page 34
2009 Microchip Technology Inc.
8.2
Using Non-Volatile EEPROM
Memory
The user can store the DAC input code (12 bits) and
power-down configuration bits (2 bits) in the internal
non-volatile EEPROM memory using the I2C write
command. The user can also read the EEPROM data
using the I2C read command. When the device is first
powered after power is shut down, the device uploads
the
EEPROM
contents
to
the
DAC
register
automatically
and
provides
the
DAC
output
immediately. This feature is very useful in applications
where the DAC device is used to provide set point or
calibration data for other devices in the application
system. The DAC will not lose the important system
operational parameters due to the system power failure
Memory” for more details of the non-volatile EEPROM
memory.
8.3
Power Supply Considerations
The power supply to the device is used for both VDD
and DAC reference voltage. Any noise induced on the
VDD line can affect on the DAC performance. Typical
application will require a bypass capacitor in order to
filter out high frequency noise on the VDD line. The
noise can be induced onto the power supply’s traces or
as a result of changes on the DAC output. The bypass
capacitor helps to minimize the effect of these noise
sources on signal integrity. Figure 8-1 shows an
example of using two bypass capacitors (a 10 F
tantalum capacitor and a 0.1 F ceramic capacitor) in
parallel on the VDD line. These capacitors should be
placed as close to the VDD pin as possible (within
4mm).
The power source should be as clean as possible. If the
application circuit has separate digital and analog
power supplies, the VDD and VSS pins of the MCP4725
should reside on the analog plane.
8.4
Layout Considerations
Inductively-coupled AC transients and digital switching
noise from other devices can affect on DAC
performance and DAC output signal integrity. Careful
board layout will minimize these effects. Bench testing
has shown that a multi-layer board utilizing a low-
inductance ground plane, isolated inputs, isolated
outputs and proper decoupling are critical to achieving
the performance that the MCP4725 is capable of
providing. Particularly harsh environments may require
shielding of critical signals. Separate digital and analog
ground planes are recommended. In this case, the VSS
pin and the ground pins of the VDD capacitors of the
MCP4725 should be terminated to the analog ground
plane.
8.5
Application Examples
The MCP4725 is a rail-to-rail output DAC designed to
operate with a VDD range of 2.7V to 5.5V. Its output
amplifier is robust enough to drive common, small-
signal loads directly, thus eliminating the cost and size
of an external buffer for most applications.
8.5.1
DC SET POINT OR CALIBRATION
A common application for the MCP4725 is a digitally-
controlled set point or a calibration of variable
parameters such as sensor offset or bias point.
Example 8-1 shows an example of the set point setting.
Since the MCP4725 is a 12-bit DAC and uses the VDD
supply as a reference source, it provides a VDD/4096 of
resolution per step.
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