Analog Output Voltage Pin (VOUT
參數(shù)資料
型號： MCP4726A0T-E/CH
廠商： Microchip Technology
文件頁數(shù)： 28/86頁
文件大?。?/td> 0K
描述： IC DAC 12BIT NV EEP I2C SOT-23-6
標準包裝： 1
設(shè)置時間： 6µs
位數(shù)： 12
數(shù)據(jù)接口： EEPROM，I²C，串行
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 單電源
功率耗散（最大）： 452mW
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： SOT-23-6
供應(yīng)商設(shè)備封裝： SOT-23-6
包裝： 標準包裝
輸出數(shù)目和類型： 1 電壓，單極
采樣率（每秒）： *
其它名稱： MCP4726A0T-E/CHDKR
MCP4706/4716/4726
DS22272C-page 34
2011-2012 Microchip Technology Inc.
3.1
Analog Output Voltage Pin (VOUT)
VOUT is the DAC analog output pin. The DAC output
has an output amplifier. VOUT can swing from
approximately 0V to approximately VDD. The full-scale
range of the DAC output is from VSS to G * VRL, where
G is the gain selection option (1x or 2x).
In Normal mode, the DC impedance of the output pin is
about 1
Ω. In Power-Down mode, the output pin is
internally connected to a known pull-down resistor of
1k
Ω, 125 kΩ, or 640 kΩ. The power-down selection
bits settings are shown in Table 4-2.
3.2
Positive Power Supply Input (VDD)
VDD is the positive supply voltage input pin. The input
supply voltage is relative to VSS.
The power supply at the VDD pin should be as clean as
possible
for
a
good
DAC
performance.
It
is
recommended to use an appropriate bypass capacitor
of about 0.1 F (ceramic) to ground. An additional
10 F
capacitor
(tantalum)
in
parallel
is
also
recommended to further attenuate high-frequency
noise present in application boards.
3.3
Ground (VSS)
The VSS pin is the device ground reference.
The user must connect the VSS pin to a ground plane
through a low-impedance connection. If an analog
ground path is available in the application Printed
Circuit Board (PCB), it is highly recommended that the
VSS pin be tied to the analog ground path or isolated
within an analog ground plane of the circuit board.
3.4
Serial Data Pin (SDA)
SDA is the serial data pin of the I2C interface. The SDA
pin is used to write or read the DAC registers and Con-
figuration bits. The SDA pin is an open-drain N-channel
driver. Therefore, it needs a pull-up resistor from the
VDD line to the SDA pin. Except for Start and Stop
conditions, the data on the SDA pin must be stable
during the high period of the clock. The high or low
state of the SDA pin can only change when the clock
signal on the SCL pin is low. Refer to Section 5.0 “I2C
Serial Interface” for more details of I2C serial interface
communication.
3.5
Serial Clock Pin (SCL)
SCL is the serial clock pin of the I2C interface. The
MCP47X6 devices act only as a slave and the SCL pin
accepts only external serial clocks. The input data from
the master device is shifted into the SDA pin on the
rising edges of the SCL clock and output from the
device occurs at the falling edges of the SCL clock. The
SCL pin is an open-drain N-channel driver. Therefore,
it needs a pull-up resistor from the VDD line to the SCL
more details about I2C serial interface communication.
3.6
Voltage Reference Pin (VREF)
This pin is used for the external voltage reference input.
The user can select VDD voltage or the VREF pin
voltage as the reference resistor ladder’s voltage
reference.
When the VREF pin signal is selected, there is an option
for this voltage to be buffered or unbuffered. This is
offered in cases where the reference voltage does not
have the current capability not to drop its voltage when
connected to the internal resistor ladder circuit.
When the VDD is selected as reference voltage, this pin
is disconnected from the internal circuit.
See
Reference Voltage” and Table 4-4 for more details on
the Configuration bits.
3.7
Exposed Pad (EP)
This pad is conductively connected to the device's
substrate. This pad should be tied to the same potential
as the VSS pin (or left unconnected). This pad could be
used to assist as a heat sink for the device when
connected to a PCB heat sink.
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