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    參數(shù)資料
    型號(hào): MCP6022-E/SN
    廠商: Microchip Technology
    文件頁(yè)數(shù): 9/42頁(yè)
    文件大?。?/td> 0K
    描述: IC OPAMP DUAL 2.5V 10MHZ 8SOIC
    標(biāo)準(zhǔn)包裝: 100
    放大器類型: 通用
    電路數(shù): 2
    輸出類型: 滿擺幅
    轉(zhuǎn)換速率: 7 V/µs
    增益帶寬積: 10MHz
    電流 - 輸入偏壓: 1pA
    電壓 - 輸入偏移: 500µV
    電流 - 電源: 1mA
    電流 - 輸出 / 通道: 30mA
    電壓 - 電源,單路/雙路(±): 2.5 V ~ 5.5 V
    工作溫度: -40°C ~ 125°C
    安裝類型: 表面貼裝
    封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
    供應(yīng)商設(shè)備封裝: 8-SOICN
    包裝: 管件
    產(chǎn)品目錄頁(yè)面: 678 (CN2011-ZH PDF)
    2009 Microchip Technology Inc.
    DS21685D-page 17
    MCP6021/1R/2/3/4
    4.0
    APPLICATIONS INFORMATION
    The MCP6021/1R/2/3/4 family of operational amplifiers
    are fabricated on Microchip’s state-of-the-art CMOS
    process. They are unity-gain stable and suitable for a
    wide range of general-purpose applications.
    4.1
    Rail-to-Rail Input
    4.1.1
    PHASE REVERSAL
    The MCP6021/1R/2/3/4 op amp is designed to prevent
    phase reversal when the input pins exceed the supply
    voltages. Figure 2-42 shows the input voltage exceed-
    ing the supply voltage without any phase reversal.
    4.1.2
    INPUT VOLTAGE AND CURRENT
    LIMITS
    The ESD protection on the inputs can be depicted as
    shown in Figure 4-1. This structure was chosen to
    protect the input transistors, and to minimize input bias
    current (IB). The input ESD diodes clamp the inputs
    when they try to go more than one diode drop below
    VSS. They also clamp any voltages that go too far
    above VDD; their breakdown voltage is high enough to
    allow normal operation, and low enough to bypass
    quick ESD events within the specified limits.
    FIGURE 4-1:
    Simplified Analog Input ESD
    Structures.
    In order to prevent damage and/or improper operation
    of these op amps, the circuit they are in must limit the
    currents and voltages at the VIN+ and VIN– pins (see
    Absolute Maximum Ratings at the beginning of
    shows the recommended approach to protecting these
    inputs. The internal ESD diodes prevent the input pins
    (VIN+ and VIN–) from going too far below ground, and
    the resistors R1 and R2 limit the possible current drawn
    out of the input pins. Diodes D1 and D2 prevent the
    input pins (VIN+ and VIN–) from going too far above
    VDD, and dump any currents onto VDD. When
    implemented as shown, resistors R1 and R2 also limit
    the current through D1 and D2.
    FIGURE 4-2:
    Protecting the Analog
    Inputs.
    It is also possible to connect the diodes to the left of
    resistors R1 and R2. In this case, current through the
    diodes D1 and D2 needs to be limited by some other
    mechanism. The resistors then serve as in-rush current
    limiters; the DC current into the input pins (VIN+ and
    VIN–) should be very small.
    A significant amount of current can flow out of the
    inputs when the common mode voltage (VCM) is below
    ground (VSS); see Figure 2-42. Applications that are
    high impedance may need to limit the useable voltage
    range.
    4.1.3
    NORMAL OPERATION
    The input stage of the MCP6021/1R/2/3/4 op amps use
    two differential CMOS input stages in parallel. One
    operates at low common mode input voltage (VCM),
    while the other operates at high VCM. WIth this topol-
    ogy, the device operates with Vcm up to 0.3V above
    VDD and 0.3V below VSS.
    4.2
    Rail-to-Rail Output
    The Maximum Output Voltage Swing is the maximum
    swing
    possible
    under
    a
    particular
    output
    load.
    According to the specification table, the output can
    reach within 20 mV of either supply rail when
    RL =10kΩ. See Figure 2-31 and Figure 2-34 for more
    information concerning typical performance.
    4.3
    Capacitive Loads
    Driving large capacitive loads can cause stability
    problems for voltage feedback op amps. As the load
    capacitance increases, the feedback loop’s phase
    margin decreases, and the closed loop bandwidth is
    reduced. This produces gain-peaking in the frequency
    response, with overshoot and ringing in the step
    response.
    Bond
    Pad
    Bond
    Pad
    Bond
    Pad
    VDD
    VIN+
    VSS
    Input
    Stage
    Bond
    Pad
    VIN
    V1
    MCP602X
    R1
    VDD
    D1
    R1 >
    VSS – (minimum expected V1)
    2mA
    R2 >
    VSS – (minimum expected V2)
    2mA
    V2
    R2
    D2
    R3
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