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| 型號(hào)： | MCP621ST-E/OT |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 17/66頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OPAMP SGL 2.5MA 20MHZ SOT23-5 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | mCal 技術(shù) |
| 放大器類型： | 通用 |
| 電路數(shù)： | 1 |
| 輸出類型： | 滿擺幅 |
| 轉(zhuǎn)換速率： | 10 V/µs |
| 增益帶寬積： | 20MHz |
| 電流 - 輸入偏壓： | 5pA |
| 電壓 - 輸入偏移： | 200µV |
| 電流 - 電源： | 2.5mA |
| 電流 - 輸出 / 通道： | 70mA |
| 電壓 - 電源，單路/雙路(±)： | 2.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SC-74A，SOT-753 |
| 供應(yīng)商設(shè)備封裝： | SOT-23-5 |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | MCP621ST-E/OTDKR |
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MCP621/1S/2/3/4/5/9
DS22188C-page 24
2009-2011 Microchip Technology Inc.
When the VCAL pin is left open, the internal resistor
divider generates a VCM_INT of approximately VDD/3,
which is near the center of the input Common mode
voltage range. It is recommended that an external
capacitor from VCAL to ground be added to improve
noise immunity.
When the VCAL pin is driven by an external voltage
source, which is within its specified range, the op amp
will have its input offset voltage calibrated at that
Common mode input voltage. Make sure that VCAL is
within its specified range.
It is possible to use an external resistor voltage divider
at the VCAL pin looks like 100 kΩ tied to VDD/3. The
parallel equivalent of R1 and R2 should be much
smaller than 100 k
Ω to minimize differences in match-
ing and temperature drift between the internal and
external resistors. Again, make sure that VCAL is within
its specified range.
FIGURE 4-2:
Setting VCM with External
Resistors.
For instance, a design goal to set VCM_INT =0.1V when
VDD = 2.5V could be met with: R1 =24.3 kΩ,
R2 =1.00 kΩ and C1 = 100 nF. This will keep VCAL
within its range for any VDD, and should be close
enough to 0V for ground-based applications.
4.2
Input
4.2.1
PHASE REVERSAL
The input devices are designed to not exhibit phase
inversion when the input pins exceed the supply
voltages.
Figure 2-41 shows
an
input voltage
exceeding both supplies with no phase inversion.
4.2.2
INPUT VOLTAGE AND CURRENT
LIMITS
The ESD protection on the inputs can be depicted as
shown in Figure 4-3. This structure was chosen to
protect the input transistors, and to minimize input bias
current (IB). The input ESD diodes clamp the inputs
when they try to go more than one diode drop below
VSS. They also clamp any voltages that go too far
above VDD; their breakdown voltage is high enough to
allow normal operation, and low enough to bypass
quick ESD events within the specified limits.
FIGURE 4-3:
Simplified Analog Input ESD
Structures.
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the currents
(and voltages) at the input pins (see Section 1.1
the recommended approach to protecting these inputs.
The internal ESD diodes prevent the input pins (VIN+
and VIN–) from going too far below ground, and the
resistors R1 and R2 limit the possible current drawn out
of the input pins. Diodes D1 and D2 prevent the input
pins (VIN+ and VIN–) from going too far above VDD, and
dump any currents onto VDD. When implemented as
shown, resistors R1 and R2 also limit the current
through D1 and D2.
FIGURE 4-4:
Protecting the Analog
Inputs.
It is also possible to connect the diodes to the left of the
resistor R1 and R2. In this case, the currents through
the diodes D1 and D2 need to be limited by some other
mechanism. The resistors then serve as in-rush current
limiters; the DC current into the input pins (VIN+ and
VIN–) should be very small.
R1
R2
VSS
VDD
VCAL
C1
MCP62X
Bond
Pad
Bond
Pad
Bond
Pad
VDD
VIN+
VSS
Input
Stage
Bond
Pad
VIN–
V1
R1
VDD
D1
R1 >
VSS – (minimum expected V1)
2mA
VOUT
R2 >
VSS – (minimum expected V2)
2mA
V2
R2
D2
MCP62X
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