參數(shù)資料
型號(hào)： MCP621T-E/MNY
廠商： Microchip Technology
文件頁(yè)數(shù)： 20/66頁(yè)
文件大小： 0K
描述： IC OPAMP SGL 20MHZ 8TDFN
標(biāo)準(zhǔn)包裝： 3,300
系列： mCal 技術(shù)
放大器類型： 通用
電路數(shù)： 1
輸出類型： 滿擺幅
轉(zhuǎn)換速率： 10 V/µs
增益帶寬積： 20MHz
電流 - 輸入偏壓： 5pA
電壓 - 輸入偏移： 200µV
電流 - 電源： 2.5mA
電流 - 輸出 / 通道： 70mA
電壓 - 電源，單路/雙路(±)： 2.5 V ~ 5.5 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 8-WFDFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 8-TDFN（2x3）
包裝： 帶卷 (TR)
2009-2011 Microchip Technology Inc.
DS22188C-page 27
MCP621/1S/2/3/4/5/9
4.4
Improving Stability
4.4.1
CAPACITIVE LOADS
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. See Figure 2-30. A unity gain buffer (G = +1)
is the most sensitive to capacitive loads, though all
gains show the same general behavior.
When driving large capacitive loads with these op
amps (e.g., > 10 pF when G = +1), a small series
resistor at the output (RISO in Figure 4-9) improves the
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The
bandwidth will be generally lower than the bandwidth
with no capacitive load.
FIGURE 4-9:
Output Resistor, RISO
Stabilizes Large Capacitive Loads.
Figure 4-10 gives recommended RISO values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN), where GN is the
circuit’s noise gain. For non-inverting gains, GN and the
Signal Gain are equal. For inverting gains, GN is
1+|Signal Gain| (e.g., -1 V/V gives GN =+2V/V).
FIGURE 4-10:
Recommended RISO Values
for Capacitive Loads.
After selecting RISO for your circuit, double check the
resulting frequency response peaking and step
response overshoot. Modify RISO’s value until the
response is reasonable. Bench evaluation and
simulations with the MCP621/1S/2/3/4/5/9 SPICE
macro model are helpful.
4.4.2
GAIN PEAKING
Figure 4-11 shows an op amp circuit that represents
non-inverting amplifiers (VM is a DC voltage and VP is
the input) or inverting amplifiers (VP is a DC voltage
and VM is the input). The capacitances CN and CG
represent the total capacitance at the input pins; they
include the op amp’s Common mode input capacitance
(CCM), board parasitic capacitance and any capacitor
placed in parallel.
FIGURE 4-11:
Amplifier with Parasitic
Capacitance.
CG acts in parallel with RG (except for a gain of +1 V/V),
which causes an increase in gain at high frequencies.
CG also reduces the phase margin of the feedback
loop, which becomes less stable. This effect can be
reduced by either reducing CG or RF.
CN and RN form a low-pass filter that affects the signal
at VP. This filter has a single real pole at 1/(2πRNCN).
The largest value of RF that should be used depends
on noise gain (see GN in Section 4.4.1 “Capacitive
Loads”) and CG. Figure 4-12 shows the maximum
recommended RF for several CG values.
FIGURE 4-12:
Maximum Recommended
RF vs. Gain.
Figures 2-37 and 2-38 show the small signal and large
signal step responses at G = +1 V/V. The unity gain
buffer usually has RF =0Ω and RG open.
Figures 2-39 and 2-40 show the small signal and large
signal step responses at G = -1 V/V. Since the noise
gain is 2 V/V and CG ≈ 10 pF, the resistors were
chosen to be RF =RG =1kΩ and RN =500Ω.
RISO
VOUT
CL
RG
RF
RN
MCP62X
1
10
100
1,000
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
Normalized Capacitance; CL/GN (F)
R
ec
o
m
en
de
d
R
IS
O
(
)
GN = +1
GN ≥ +2
1p
100p
1n
10n
10p
VP
RF
VOUT
RN
CN
VM
RG
CG
MCP62X
1.E+02
1.E+03
1.E+04
1.E+05
110
100
Noise Gain; GN (V/V)
M
axi
m
u
m
R
eco
m
en
ded
R
F
(
)
GN > +1 V/V
100
10k
100k
1k
CG = 10 pF
CG = 32 pF
CG = 100 pF
CG = 320 pF
CG = 1 nF
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