Recommended RISO V" />
參數(shù)資料
型號(hào)： MCP6N11-002E/SN
廠商： Microchip Technology
文件頁(yè)數(shù)： 26/50頁(yè)
文件大?。?/td> 0K
描述： IC AMP INSTR RRIO 8SOIC
標(biāo)準(zhǔn)包裝： 100
放大器類型： 儀表
電路數(shù)： 1
輸出類型： 滿擺幅
轉(zhuǎn)換速率： 9 V/µs
增益帶寬積： 1MHz
電流 - 輸入偏壓： 10pA
電壓 - 輸入偏移： 2000µV
電流 - 電源： 800µA
電流 - 輸出 / 通道： 30mA
電壓 - 電源，單路/雙路(±)： 1.8 V ~ 5.5 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 8-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 8-SOICN
包裝： 管件
MCP6N11
DS25073A-page 32
2011 Microchip Technology Inc.
FIGURE 4-9:
Recommended RISO Values
for Capacitive Loads.
After selecting RISO for your circuit, double check the
resulting frequency response peaking and step
response overshoot on the bench. Modify RISO’s value
until the response is reasonable.
4.3.3
GAIN RESISTORS
Figure 4-10 shows a simple gain circuit with the INA’s
input capacitances at the feedback inputs (VREF and
VFG). These capacitances interact with RG and RF to
modify the gain at high frequencies. The equivalent
capacitance acting in parallel to RG is CG =CDM +CCM
plus any board capacitance in parallel to RG. CG will
cause an increase in GDM at high frequencies, which
reduces the phase margin of the feedback loop (i.e.,
reduce the feedback loop's stability).
FIGURE 4-10:
Simple Gain Circuit with
Parasitic Capacitances.
In this data sheet, RF +RG =10 kΩ for most gains (0Ω
for GDM = 1); see Table 1-6. This choice gives good
Phase Margin. In general, RF (Figure 4-10) needs to
meet the following limits to maintain stability:
EQUATION 4-12:
4.3.4
SUPPLY BYPASS
With these INAs, the power supply pin (VDD for single
supply) should have a local bypass capacitor (i.e.,
0.01 F to 0.1 F) within 2 mm for good high frequency
performance. Surface mount, multilayer ceramic
capacitors, or their equivalent, should be used.
These INAs require a bulk capacitor (i.e., 1.0 F or
larger) within 100 mm, to provide large, slow currents.
This bulk capacitor can be shared with other nearby
analog parts as long as crosstalk through the supplies
does not prove to be a problem.
1.E+03
1.E+04
o
mmended
R
ISO
()
10k
1k
1.E+02
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
Rec
o
Normalized Load Capacitance;
C
L GMIN/GDM (F)
100
100p
1n
10n
100n
1μ
G
MIN = 1 to 10
G
MIN = 100
VOUT
V1
VDD
V2
VREF
VFG
RF
RG
CDM
CCM
U1
MCP6N11
Where:
α≤ 0.25
GDM ≥ GMIN
fGBWP = Gain Bandwidth Product
CG = CDM + CCM + (PCB stray capacitance)
R
F
0
=
For G
DM =1:
R
F
αG
DM
2
πf
GBWPCG
------------------------------
<
For G
DM >1:
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