參數(shù)資料
型號: MCR705JP7CDWE
廠商: Freescale Semiconductor
文件頁數(shù): 15/164頁
文件大?。?/td> 0K
描述: MCU 8BIT 224B RAM 28-SOIC
標(biāo)準(zhǔn)包裝: 26
系列: HC05
核心處理器: HC05
芯體尺寸: 8-位
速度: 2.1MHz
連通性: SIO
外圍設(shè)備: POR,溫度傳感器,WDT
輸入/輸出數(shù): 22
程序存儲器容量: 6KB(6K x 8)
程序存儲器類型: OTP
RAM 容量: 224 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
包裝: 管件
Output Compare Registers
MC68HC705JJ7 MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
111
Figure 11-8. Timer Output Compare Block Diagram
Writing to the OCRH before writing to the OCRL inhibits timer compares until the OCRL is written.
Reading or writing to the OCRL after reading the TCR will clear the output compare flag bit (OCF). The
output compare OLVL state will be clocked to its output latch regardless of the state of the OCF.
To prevent OCF from being set between the time it is read and the time the output compare registers are
updated, use this procedure:
1.
Disable interrupts by setting the I bit in the condition code register.
2.
Write to the OCRH. Compares are now inhibited until OCRL is written.
3.
Read the TSR to arm the OCF for clearing.
4.
Enable the output compare registers by writing to the OCRL. This also clears the OCF flag bit in
the TSR.
5.
Enable interrupts by clearing the I bit in the condition code register.
A software example of this procedure is shown in Table 11-1.
Address:
$0016
Bit 7
654321
Bit 0
Read:
Bit 15
14
13
12
11
10
9
Bit 8
Write:
Reset:
Unaffected by reset
Address:
$0017
Bit 7
654321
Bit 0
Read:
Bit 7
654321
Bit 0
Write:
Reset:
Unaffected by reset
Figure 11-9. Output Compare Registers (OCRH and OCRL)
OCIE
OCRH ($0016)
16-BIT COUNTER
÷ 4
INTERNAL
(OSC
÷ 2)
TIMER CONTROL REG.
TIMER
REQUEST
OUTPUT COMPARE
RESET
CLOCK
INTERRUPT
OCRL ($0017)
OCF
TIMER STATUS REG.
$0012
$0013
INTERNAL
$FFFC
DATA
R/W
OCRH
R/W
OCRL
BUS
OL
VL
PB4
AN4
TCMP
EDGE
SELECT
DETECT
LOGIC
OL
VL
16-BIT COMPARATOR
(OCF)
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