參數(shù)資料
型號(hào)： MCZ33291LEG
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： Eight-Output Switch with Serial Peripheral Interface I/O
中文描述： 8輸出開(kāi)關(guān)串行外設(shè)接口的I / O
文件頁(yè)數(shù)： 8/25頁(yè)
文件大?。?/td> 389K
代理商： MCZ33291LEG
Analog Integrated Circuit Device Data
Freescale Semiconductor
8
33291L
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics
Characteristics noted under conditions 4.5 V
≤
V
DD
≤
5.5 V, 9.0 V
≤
V
PWR
≤
16 V, -40
°
C
≤
T
A
≤
125
°
C, unless otherwise noted.
Typical values noted reflect the approximate parameter mean at T
A
= 25
°
C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT TIMING
Output Rise Time (V
PWR
= 13 V, R
L
= 26
)
(26)
Output Fall Time (V
PWR
= 13 V, R
L
= 26
)
(26)
Output Turn-ON Delay Time (V
PWR
= 13 V, R
L
= 26
)
(27)
Output Turn-OFF Delay Time (V
PWR
= 13 V, R
L
= 26
)
(28)
Output Short Fault Disable Report Delay
(29)
SFPD = 0.2 x V
DD
t
r
0.4
5.0
20
μ
s
t
f
0.4
5.0
20
μ
s
t
dly (on)
1.0
15
50
μ
s
t
dly (off)
1.0
15
50
μ
s
t
dly (sf)
70
150
250
μ
s
Output OFF Fault Report Delay
(30)
SFPD = 0.2 x V
DD
t
dly (off)
70
150
250
μ
s
DIGITAL INTERFACE TIMING
Required Low State Duration for
RST
(V
IL
< 0.2 V
DD
)
(31)
t
w(RST)
–
50
167
ns
Falling Edge of
CS
to Rising Edge of SCLK (Required Setup Time)
t
lead
–
50
167
ns
Falling Edge of SCLK to Rising Edge of
CS
(Required for Setup Time)
t
lag
–
50
167
ns
SI to Falling Edge of SCLK (Required for Setup Time)
t
SI (su)
–
25
83
ns
Falling Edge of SCLK to SI (Required for Hold Time)
t
SI (hold)
–
25
83
ns
SO Rise Time (C
L
= 200 pF)
t
r (SO)
–
25
50
ns
SO Fall Time (C
L
= 200 pF)
SI,
CS
, SCLK, Incoming Signal Rise Time
(32)
t
f (SO)
–
25
50
ns
t
r (SI)
–
–
50
ns
SI,
CS
, SCLK, Incoming Signal Fall Time
(32)
t
f (SI)
–
–
50
ns
Time from Falling Edge of
CS
to SO Low Impedance
(33)
t
SO(en)
–
–
110
ns
Time from Rising Edge of
CS
to SO High Impedance
(34)
t
SO(dis)
–
–
110
ns
Time from Rising Edge of SCLK to SO Data Valid
(35)
0.2 V
DD
≤
SO
≥
0.8 V
DD
, C
L
= 200 pF
t
valid
–
65
105
ns
Notes
26.
27.
28.
29.
Output Rise and Fall time respectively measured across a 26
resistive load at 10% to 90% and 90% to 10% voltage points.
Output Turn-ON Delay time measured from 50% rising edge of
CS
to 90% of Output OFF voltage (V
PWR
) with R
L
= 26
resistive load.
Output Turn-OFF Delay time measured from 50% rising edge of
CS
to 10% of Output OFF voltage (V
PWR
) with R
L
= 26
resistive load.
Propagation time of Short Fault Disable Report measured from 50% rising edge of
CS
to 10% Output OFF voltage (V
PWR
), V
PWR
=
6.0 V and SFPD = 2.0 x V
DD
.
Output OFF Fault Report Delay measured from 50% rising edge of
CS
to 10% rising edge of Output OFF voltage (V
PWR
).
RST
Low duration measured with outputs enabled and going to OFF or disabled condition.
Rise and Fall time of incoming SI,
CS
, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
Time required for output status data to be available for use at the SO pin.
Time required for output status data to be terminated at the SO pin.
Time required to obtain valid data out from SO following the rise of SCLK. See
Figure 6
, page
9
.
30.
31.
32.
33.
34.
35.
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