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| 型號： | MCZ33742SEGR2 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 25/71頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SYSTEM BASIS CHIP CAN 28-SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 應(yīng)用： | 自動 |
| 電流 - 電源： | 42mA |
| 電源電壓： | 5.5 V ~ 18 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC W |
| 包裝： | 帶卷 (TR) |
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Analog Integrated Circuit Device Data
Freescale Semiconductor
31
33742
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Figure 12. RST and WDOG Output Operation
WAKE-UP CAPABILITIES
Several wake-up capabilities are available to the SBC when it is in Sleep or Stop mode. When a wake-up has occurred, the
wake-up event is stored in the Wake-up Register (WUR) or the CAN register and read by the MCU to determine the wake-up
source. The wake-up options are selectable through SPI while the 33742 is in Normal or Standby mode and prior to entering low
power modes (Sleep or Stop mode). When a wake-up occurs in Sleep mode, the SBC reactivates the VDD supply. It generates
an interrupt if a wake-up occurs from Stop mode.
WAKE-UP FROM WAKE-UP INPUTS (L0:L3) WITHOUT CYCLIC SENSE
The wake-up lines are used to determine the state of external switches and if changes occurred to wake up the MCU (in Sleep
or Stop modes). The wake-up pins L0:L3 are able to handle up to 40 VDC. The internalize” threshold is 3.0 V typical, and these
inputs can be used as an input port expander. The wake-up input states are read through SPI (WUR register).
In order to select and activate direct wake-up from the L0:L3 inputs, the WUR register must be configured with the appropriate
level sensitivity. Additionally, the Low Power Control (LPC) Register must be configured with 0xx0 data (bits LX2HS and
HSAUTO are set to 0).
The sensitivity of the L0:L3 inputs is selected by the WUR register. Level sensitivity is configured by L0:L3 input pairs: L0 and
L1 level sensitivity are configured together, while L2 and L3 are configured together.
CYCLIC SENSE WAKE-UP (CYCLIC SENSE TIMER AND WAKE-UP INPUTS L0:L3)
The 33742 can wake up upon state change of one of the four wake-up input lines (L0:L3). The external pull-up or pull-down
resistor of the switches associated with the wake-up input lines can be biased from the HS VSUP switch. The HS switch is
activated in Sleep or Stop modes from an internal timer. Cyclic Sense and Forced Wake-up are exclusive states. If Cyclic Sense
is enabled, Forced Wake-up cannot be enabled.
VSUP
SPI
Mode
RESET
N-Request
Normal
Wake-up event
Sleep
VSUP
INT
SPI
Mode
N-Request
Normal
Wake-up event
Stop
Device is in sleep mode
Device is in stop mode
VSUP
SPI
Mode
RESET
N-Request
Normal
Power up
Device power up
RST
WDOG
VDD
SPI
SPI CS
Watchdog
Period
RST
WDOG
VDD
WDOG
VDD
RST
WDOG
VDD
Device is in Normal mode, W/D refresh failure
Legend: TIM1 register write
Watchdog refresh failure
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