LOGIC COMMANDS AND REGISTERS INTERRUPT REGI" />
參數(shù)資料
型號(hào)： MCZ33742SEGR2
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 52/71頁(yè)
文件大?。?/td> 0K
描述： IC SYSTEM BASIS CHIP CAN 28-SOIC
標(biāo)準(zhǔn)包裝： 1,000
應(yīng)用： 自動(dòng)
電流 - 電源： 42mA
電源電壓： 5.5 V ~ 18 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 28-SOIC W
包裝： 帶卷 (TR)
Analog Integrated Circuit Device Data
56
Freescale Semiconductor
33742
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
INTERRUPT REGISTER (INTR)
Tables 41 through 43 contain the Interrupt Register information. The INTR register allows masking or enabling the interrupt
source. A read operation identifies the interrupt source. Table 43 provides status bit information. The status bits of the INTR
register content are copies of the IOR, CAN, TIM, and LPC registers status content. To clear the Interrupt Register bits, the IOR,
CAN, TIM, and/or LPC registers must be cleared (read register) and the recovery condition must occur. Errors bits are latched
in the CAN register and the IOR register.
When the mask bit is set, the INT pin goes LOW if the appropriate condition occurs. Upon a wake-up condition from Stop mode
due to over-current detection (IDDS-WU1 or IDDS-WU2), an INT pulse is generated; however, INTR register content remains at 0000
(not bit set into the INTR register).
Table 41. Interrupt Register
INTR
R/W
D3
D2
D1
D0
$111b
W
VSUPLOW
HSOT-V2LOW(67)
V1TEMP
CANF
R
VSUPLOW
HSOT
V1TEMP
CANF
Reset Value
–
0
Reset Condition (Write)(68)
–
POR, RST
Notes
67.
If only HSOT - V2LOW interrupt is selected (only bit D2 set in INTR register), reading INTR register bit D2 leads to two possibilities:
1. Bit D2 = 1: Interrupt source is HSOT.
2. Bit D2 = 0: Interrupt source is V2LOW.
HSOT and V2LOW bits status are available in the IOR register.
68.
See Table 13, page 46, for definitions of reset conditions.
Table 42. Interrupt Register Control Bits
Name
Description
CANF
Mask bit for CAN failures.
VDDTEMP
Mask bit for VDD medium temperature (pre-warning).
HSOT - V2LOW
Mask bit for HS over-temperature AND V2LTH < 4.0 V.
VSUPLOW
Mask bit for VBF(EW) < 5.8 V.
Table 43. Interrupt Register Status Bits
Name
Logic
Description
VSUPLOW
0
No VBF(EW) < 5.8 V.
1
VBF(EW) < 5.8 V.
HSOT
0
No HS over-temperature.
1
HS over-temperature.
VDDTEMP
0
No VDD medium temperature (pre-warning).
1
VDD medium temperature (pre-warning).
CANF
0
No CAN failure.
1
CAN failure.
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