DETAIL OPERATION COMPLETE SPI OPERATION" />
參數(shù)資料
型號(hào): MCZ33905BS5EKR2
廠(chǎng)商: Freescale Semiconductor
文件頁(yè)數(shù): 70/106頁(yè)
文件大?。?/td> 0K
描述: IC SBC CAN HS 5.0V 32SOIC
標(biāo)準(zhǔn)包裝: 1,000
應(yīng)用: 系統(tǒng)基礎(chǔ)芯片
接口: CAN,LIN
電源電壓: 5.5 V ~ 28 V
封裝/外殼: 32-BSOP(0.295",7.50mm 寬)裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 32-SOICW 裸露焊盤(pán)
包裝: 帶卷 (TR)
安裝類(lèi)型: 表面貼裝
Analog Integrated Circuit Device Data
66
Freescale Semiconductor
33903/4/5
SERIAL PERIPHERAL INTERFACE
DETAIL OPERATION
COMPLETE SPI OPERATION
Table 14 is a compiled view of all the SPI capabilities and
options. Both MOSI and MISO information are described.
Note: P = 0 if parity bit is not selected or parity = 0. P = 1 if parity
is selected and parity = 1.
PARITY BIT 8
Calculation
The parity is used for the write-to-register command (bit
15,14 = 01). It is calculated based on the number of logic one
contained in bits 15-9,7-0 sequence (this is the entire 16 bits
of the write command except bit 8).
Bit 8 must be set to 0 if the number of 1 is odd.
Bit 8 must be set to 1if the number of 1 is even.
Examples 1:
MOSI [bit 15-0] = 01 00 011 P 01101001, P should be 0,
because the command contains 7 bits with logic 1.
Thus the Exact command will then be:
MOSI [bit 15-0] = 01 00 011 0 01101001
Examples 2:
MOSI [bit 15-0] = 01 00 011 P 0100 0000, P should be 1,
because the command contains 4 bits with logic 1.
Thus the Exact command will then be:
MOSI [bit 15-0] = 01 00 011 1 0100 0000
Parity Function Selection
All SPI commands and examples do not use parity
functions.
The parity function is optional. It is selected by bit 6 in INIT
MISC register.
If parity function is not selected (bit 6 of INIT MISC = 0),
then Parity bits in all SPI commands (bit 8) must be “0”.
Table 14. SPI Capabilities with Options
Type of Command
MOSI/
MISO
Control bits
[15-14]
Address
[13-9]
Parity/Next
bits [8]
Bit 7
Bits [6-0]
Read back of “device control bits” (MOSI bit 7 = 0)
OR
Read specific device information (MOSI bit 7 = 1)
MOSI
00
address
1
0
000 0000
MISO
Device Fixed Status (8 bits)
Register control bits content
MOSI
00
address
1
000 0000
MISO
Device Fixed Status (8 bits)
Device ID and I/Os state
Write device control bit to address selected by bits
(13-9).
MISO return 16 bits device status
MOSI
01
address
(note)
Control bits
MISO
Device Fixed Status (8 bits)
Device Extended Status (8 bits)
Reserved
MOSI
10
Reserved
MISO
Reserved
Read device flags and Wake-up flags, from
register address (bit 13-9), and sub address (bit 7).
MISO return fixed device status (bit 15-8) + flags
from the selected address and sub-address.
MISO
11
address
Reserved
0
Read of device flags form a register address,
and sub address LOW (bit 7)
MOSI
Device Fixed Status (8 bits)
Flags
MISO
11
address
1
Read of device flags form a register address,
and sub address HIGH (bit 7)
MOSI
Device Fixed Status (8 bits)
Flags
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