DETAIL OF CONTROL BITS AND REGISTER MAPPING" />
參數(shù)資料
型號： MCZ33905BS5EKR2
廠商： Freescale Semiconductor
文件頁數(shù)： 81/106頁
文件大?。?/td> 0K
描述： IC SBC CAN HS 5.0V 32SOIC
標(biāo)準(zhǔn)包裝： 1,000
應(yīng)用： 系統(tǒng)基礎(chǔ)芯片
接口： CAN，LIN
電源電壓： 5.5 V ~ 28 V
封裝/外殼： 32-BSOP（0.295"，7.50mm 寬）裸露焊盤
供應(yīng)商設(shè)備封裝： 32-SOICW 裸露焊盤
包裝： 帶卷 (TR)
安裝類型： 表面貼裝
Analog Integrated Circuit Device Data
76
Freescale Semiconductor
33903/4/5
SERIAL PERIPHERAL INTERFACE
DETAIL OF CONTROL BITS AND REGISTER MAPPING
Prior to enter in LP VDD ON or LP VDD OFF, the Wake-up
flags must be cleared or read.
This is done by the following SPI commands (See Table
0xE100 for CAN Wake-up clear
0xE380 for I/O Wake-up clear
0xE700 for LIN1 Wake-up clear
0xE900 for LIN2 Wake-up clear
If Wake-up flags are not cleared, the device will enter into
the selected LP mode and immediately Wake-up. In addition,
the CAN failure flags (i.e. CAN_F and CAN_UF) must be
cleared in order to meet the low power current consumption
specification. This is done by the following SPI command:
0xE180 (read CAN failure flags)
When the device is in LP VDD ON mode, the Wake-up by
a SPI command uses a write to “Normal Request mode”,
0x5C10.
Mode Register Features
The mode register includes specific functions and a “global
SPI command” that allow the following:
- read device current mode
- read device Debug status
- read state of SAFE pin
- leave Debug state
- release or turn off SAFE pin
- read a 3 bit Random Code to enter in LP mode
These global commands are built using the MODE register
address bit [13-9], along with several combinations of bit [15-
14] and bit [7]. Note, bit [8] is always set to 1.
Table 28. LP VDD OFF Selection and FWU / Cyclic Sense Selection
b7, b6, b5, b4, b3
FWU
Cyclic Sense
0 1100
OFF
0 1101
OFF
ON
0 1110
ON
OFF
0 1111
ON
Table 29. LP VDD ON Selection and Operation Mode
b7, b6, b5, b4, b3
FWU
Cyclic Sense
Cyclic INT
Watchdog
1 0000
OFF
1 0001
OFF
ON
1 0010
OFF
ON
OFF
1 0011
OFF
ON
1 0100
OFF
ON
OFF
1 0101
OFF
ON
OFF
ON
1 0110
OFF
ON
OFF
1 0111
OFF
ON
1 1000
ON
OFF
1 1001
ON
OFF
ON
1 1010
ON
OFF
ON
OFF
1 1011
ON
OFF
ON
1 1100
ON
OFF
1 1101
ON
OFF
ON
1 1110
ON
OFF
1 1111
ON
b2, b1, b0
Random Code inverted, these 3bits are the inverted bits obtained from the previous SPI command.
The usage of these bits are optional and must be previously selected in the INIT MISC register [See
bit 7 (LPM w RNDM) in Table 20]
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