Analog Integrated Circuit Device Data
Freescale Semiconductor
16
33976
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
changed by command. Velocities can range from position 1
(00000001) to position 225 (11111111).
Addresses 010 and 011 — Gauge 0/1 Position Registers
(POS0R, POS1R)
SI Address 010 (Gauge 0 Position Register) and SI
Address 011 (Gauge 1 Position Register) Register bits PO
11: PO0 are written to when communicating the desired
pointer positions.
Commanded positions can range from 0 to 4095. The D12
bit is used to disable the damping (i.e., hold counts) for each
respective gauge. This feature allows the user to easily turn
on and off the damping that was configured with the
RMPSELR. Disabling the hold counts allows the pointer to
decelerate to the commanded position, as fast as possible
down the velocity ramp. When disabled, the acceleration and
deceleration of the pointer are symmetrical.
The bits in
Table 9
are
write-only
.
HE0 12 (D12) — This bit is used to disable the damping
(i.e., hold counts) for Gauge 0 (1 = Damping disabled;
0 = Damping enabled).
P0 11:P0 0 (D11:D0) — Desired pointer position of
Gauge 0. Pointer positions can range from 0
(000000000000) to position 4095 (111111111111). For a
step motor requiring 12 microsteps per degree of pointer
movement, the maximum pointer sweep is 341.25
°.
.
Table 10. Gauge 1 Position Register (POS1R)
The bits in
Table 10
are
write-only
.
HE1 12 (D12) — This bit is used to disable the damping
(i.e., hold counts) for Gauge 1 (1 = Damping disabled;
0 = Damping enabled).
P1 11:P1 0 (D11:D0) — Desired pointer position of
Gauge 1. Pointer positions can range from 0
(000000000000) to position 4095 (111111111111). For a
step motor requiring 12 microsteps per degree of pointer
movement, the maximum pointer sweep is 341.25
°
(4095 ÷ 12)
.
Address 100 — Gauge Return to Zero Register (RTZR)
Gauge Return to Zero Register (RTZR) (refer to
Table 11
,
page
17
) is written to return the gauge pointers to the zero
position. During an RTZ event, the pointer is returned to zero
using full steps, where only one coil is driven at any point in
time. The back electromotive force (EMF) signal present on
the non-driven coil is integrated and its results are stored in
an accumulator.
A logic [1] written to bit RZ1 enables a Return to Zero for
Gauge 0 if RZ0 is logic [0], and Gauge 1 if RZ0 is logic [1],
respectively. Similarly, a logic [0] written to bit RZ1 disables a
Return to Zero for Gauge 0 when RZ0 is logic [0], and
Gauge 1 when RZ0 is logic [1], respectively.
Bits D12:D5 and D3:D2 must be at logic [0] for valid RTZR
commands.
Bit RZ4 is used to enable an unconditional RTZ event. A
logic [0] results in a typical RTZ event, automatically
providing a Stop when a stall condition is detected. A logic [1]
will result in RTZ movement, causing a Stop if a logic [0] is
written to bit RZ0. This feature is useful during development
and characterization of RTZ requirements.
Table 9. Gauge 0 Position Register (POS0R)
Address 010
Bits
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Read
–
–
–
–
–
–
–
–
–
–
–
–
–
Write
HE012
P0 11
P0 10
P0 9
P0 8
P0 7
P0 6
P0 5
P0 4
P0 3
P02
P01
P0 0
Address 011
Bits
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Read
–
–
–
–
–
–
–
–
–
–
–
–
–
Write
HE112
P1 11
P1 10
P1 9
P1 8
P1 7
P1 6
P1 5
P1 4
P1 3
P1 2
P1 1
P1 0