參數(shù)資料
型號(hào): MCZ33976EG
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: Dual Gauge Driver with Configurable esponse Time
中文描述: 雙計(jì)驅(qū)動(dòng)器,可配置esponse時(shí)間
文件頁數(shù): 21/41頁
文件大?。?/td> 551K
代理商: MCZ33976EG
Analog Integrated Circuit Device Data
Freescale Semiconductor
21
33976
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
SO Communication
When the
CS
pin is pulled low, the internal status register,
as configured with the PECCR command bits PE11:PE8, is
loaded into the output register and the data is clocked out
MSB (OD15) first. Following a
CS
transition 0 to 1, the device
determines if the shifted-in message was of a valid length (a
valid message length is one that is greater than 0 bits and a
multiple of 16 bits) and, if so, latches the incoming data into
the appropriate registers.
At this time, the SO pin is tri-stated and the status register
is now able to accept new status information. Fault status
information will be latched and held until the Device Status
Output register is selected and it is clocked out via the SO. If
the message length was determined to be invalid, the fault
information will not be cleared and will be transmitted again
during the next valid SPI message. Pointer status information
bits (e.g., pointer position, velocity, and commanded position
status) will always reflect the real time state of the pointer.
Any bits clocked out of the SO pin after the first 16 are
representative of the initial message bits clocked into the SI
pin since the
CS
pin first transitioned to a logic [0]. This
feature is useful for daisy-chaining devices as well as
message verification.
As described above, the last valid write to bits PE11:PE8
of the PECCR command determines the nature of the status
data that is clocked out of the SO pin.
There are five different types of status information
available:
1. Device Status (refer to
Table 20
, page
21
)
2. RTZ Accumulator Status (refer to
Table 22
, page
23
)
3. Gauge 0 Pointer Position Status (refer to
Table 24
,
page
24
)
4. Gauge 1 Pointer Position Status (refer to
Table 26
,
page
24
)
5. Gauge 1 and 2 Pointer Velocity Status (refer to
Table 28
, page
24
)
Once a specific status type is selected, it will not change
until either the PECCR command bits PE11:PE8 (D11:D8)
are written to select another or the device is reset. Each of the
Status types and the PECCR bit necessary to select them are
described in the following paragraphs.
Device Status Information
Most recent valid PECCR command resulting in the
Device Status output:
The bits in
Table 20
are
read-only
bits.
DIR1 (OD15) — This bit indicates the direction Gauge 1
pointer is moving.
0 = Toward position 0
1 = Away from position 0
DIR0 (OD14) — This bit indicates the direction Gauge 0
pointer is moving.
0 = Toward position 0
1 = Away from position 0
Table 18. Truncated Velocity Steps
RS3
RS2
RS1
RS0
Zero Velocity
Position # (RS)
0
0
0
0
0
0
0
0
1
1
0
0
1
0
2
0
0
1
1
3
0
1
0
0
4
0
1
0
1
5
0
1
1
0
6
0
1
1
1
7
1
0
0
0
8
1
0
0
1
9
1
0
1
0
10
1
0
1
1
11
1
1
0
0
12
1
1
0
1
13
1
1
1
0
14
1
1
1
1
15
Table 19.
D11
D10
D9
D8
0
x
x
x
x = Don’t care.
Table 20. Device Status Output Register
Bits
OD15
OD14
OD13
OD12
OD11
OD10
OD9
OD8
OD7
OD6
OD5
OD4
OD3
OD2
OD1
OD0
Read
DIR1
DIR0
0POS1 0POS0 CMD1 CMD0
OV
UV
CAL
OVUV MOV1 MOV0
RTZ1
RTZ0
OT1
OT0
Write
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參數(shù)描述
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