Analog Integrated Circuit Device Data
Freescale Semiconductor
20
34701
FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
Figure 15. LDO Converter Over-current Protection
The output voltage VOUT can be adjusted by means of an
external resistor divider connected to the feedback control
pin INV. The switching regulator output voltage can be
adjusted in the range of 0.8V to V
IN
- buck dropout voltage.
Power-up, power-down, and fault management are
coordinated with the linear regulator.
SWITCHER OSCILLATOR
A 300kHz (default) oscillator sets the switching frequency
of the buck regulator. The frequency of the oscillator can be
adjusted between 200kHz and 400kHz by an optional
external resistor R
F
connected from the FREQ pin of the
integrated circuit to ground. See
Figure 6
on page 14 for
frequency resistor selection.
The CLKSYN pin can be configured as either an oscillator
output when the CLKSEL pin is left open or as a
synchronization input when the CLKSEL pin is grounded.
The oscillator output signal is a square wave logic signal with
50% duty cycle, 180 degrees out-of-phase with the internal
clock signal. This allows opposite phase synchronization of
two 34702 devices.
When the CLKSYN pin is used as a synchronization input
(CLKSEL pin grounded), the external resistor R
F
chosen
from the chart in
Figure 6
should be used to synchronize the
internal slope compensation ramp to the external clock.
Operation is only recommended between 200kHz and
400kHz. The supplied synchronization signal does not need
to be 50% duty cycle. Minimum pulse width is 1.0μs.
LOW DROPOUT LINEAR REGULATOR (LDO)
The adjustable low dropout linear regulator (LDO) is
capable of supplying a 1.0A output current. It has a current
limit with retry capability. When the voltage measured across
the current sense resistor reaches the 50mV threshold, the
control circuit limits the current for 10ms. If the over-current
condition still exists, the linear regulator is turned off and the
retry timer starts to time out. When the timer expires after
100ms, the LDO tries to power-up again for 10ms, repeatedly
checking for the over-current condition. The current limit of
the LDO can be set by using the following formula:
I
LIM
= 50mV / RS
Where R
S
is the LDO current sense resistor, connected
between the CS pin and the LDO pin output (see
Figure 33
on page
34
), and 50mV is the typical value of the LDO current
sense comparator threshold voltage.
When no current sense resistor is used, it is still possible
to detect the over-current condition by tying the current sense
pin CS to the VBST voltage. In this case, the over-current
condition is sensed by saturation of the linear regulator driver
buffer.
The output voltage of the LDO can be adjusted by means
of an external resistor divider connected to the feedback
control pin LFB. The linear regulator output voltage can be
adjusted in the range of 0.8V to V
IN
- LDO dropout voltage.
Power-up, power-down, and fault management are
coordinated with the switching regulator.
POWER SEQUENCING VOLTAGE MARGINING
WATCHDOG TIMER
A watchdog function is available via I
2
C bus
communication. It is possible to select either window
watchdog or timeout watchdog operation, as illustrated in
Figure 16
.
Watchdog timeout starts when the watchdog function is
activated via I
2
C bus sending a watchdog programming
command byte, thus determining watchdog operation
(window or timeout) and period duration (refer to
Table 8
,
page
27
). If the watchdog is cleared by receiving a new
watchdog programming command through the I
2
C bus, the
watchdog timer is reset and the new timeout period begins. If
the watchdog time expires, the
RST
will become active
(LOW) for a time determined by the RC components of the
RT timer plus 10ms. After a watchdog timeout, the function is
no longer active.
Figure 16. Watchdog Operation
50% of Watchdog Period
Watchdog Period
Timing Selected via 12C Bus – See Table 4
Window Watchdog
Watchdog Closed
No Watchdog Clear Allowed
Window Open
for Watchdog Clear
Window Open for Watchdog Clear
Watchdog Period
Timing Selected via I
2
C Bus – See Table 4
Time-Out Watchdog