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MD1210
NR013105
4
Detailed Block Diagram
Application Information
For proper operation of the MD1210, low inductance
bypass capacitors should be used on the various supply
pins. The GND input pin should be connected to the
digital ground. The INA, INB, and OE pins should be
connected to their logic source with a swing of GND to
logic level high which is 1.2 to 5.0 volts. Good trace
practices should be followed corresponding to the desired
operating speed. The internal circuitry of the MD1210 is
capable of operating up to 100MHz, with the primary
speed limitation being the loading effects of the load
capacitance. Because of this speed and the high
transient currents that result with capacitive loads, the
bypass capacitors should be as close to the chip pins as
possible. Unless the load specifically requires bipolar
drive, the V
SS
1, V
SS
2, and V
L
pins should have low
inductance feed-through connections directly to a ground
plane. If these voltages are not zero, then they need
bypass capacitors in a manner similar to the positive
power supplies. The power connections V
DD
1 and V
DD
2
should have a ceramic bypass capacitor to the ground
plane with short leads and decoupling components to
prevent resonance in the power leads. A common
capacitor and voltage source may be used for these two
pins, which should always have the same DC voltage
applied. For applications sensitive to jitter and noise,
separate decoupling networks may be used for V
DD
1 and
V
DD
2.
The supplied voltages of V
H
and V
L
determine the output
logic levels. These two pins can draw fast transient
currents of up to 2.0A, so they should be provided with an
appropriate bypass capacitor located next to the chip
pins. A ceramic capacitor of up to 1.0μF may be
appropriate, with a series ferrite bead to prevent
resonance in the power supply lead coming to the
capacitor. Pay particular attention to minimizing trace
lengths and using sufficient trace width to reduce
inductance. Surface mount components are highly
recommended. Since the output impedance of this driver
is very low, in some cases it may be desirable to add a
small series resistor in series with the output signal to
obtain better waveform integrity at the load terminals.
This will of course reduce the output voltage slew rate at
the terminals of a capacitive load.
Pay particular attention to the parasitic coupling from the
driver output to the input signal terminals. This feedback
may cause oscillations or spurious waveform shapes on
the edges of signal transitions. Since the input operates
with signals down to 1.2V even small coupled voltages
may cause problems. Use of a solid ground plane and
good power and signal layout practices will prevent this
problem. Be careful that the circulating ground return
current from a capacitive load cannot react with common
inductance to cause noise voltages in the input logic
circuitry.
V
DD
2
V
H
V
L
INA
OUTA
INB
Level
Shifter
OE
V
SS
2
V
L
OUTB
V
SS
2
Level
Shifter
Level
Shifter
V
DD
2
V
H
V
SS
1
GND
V
DD
1
SUB