參數(shù)資料
型號: MD1810K6-G
廠商: SUPERTEX INC
元件分類: MOSFETs
英文描述: HIGH SPEED QUAD MOSFET DRIVER
中文描述: 2 A AND GATE BASED MOSFET DRIVER, QCC16
封裝: 4 X 4 MM, 0.9 HEIGHT, GREEN, QFN-16
文件頁數(shù): 6/7頁
文件大小: 523K
代理商: MD1810K6-G
6
NR090105
MD1810
Application Information
For proper operation of the MD1810, low inductance bypass
capacitors should be used on the various supply pins. The GND
pin should be connected to the logic ground. The INA, INB INC,
IND, and OE pins should be connected to a logic source with a
swing of GND to V
, where V
is 1.2 to 5.0 volts. Good trace
practices should be followed corresponding to the desired operating
speed. The internal circuitry of the MD1810 is capable of operating
up to 100MHz, with the primary speed limitation being the loading
effects of the load capacitance. Because of this speed and the
high transient currents that result with capacitive loads, the bypass
capacitors should be as close to the chip pins as possible. Unless
the load specifically requires bipolar drive, the V
, and V
pins
should have low inductance feed-through connections directly to a
ground plane. If these voltages are not zero, then they need bypass
capacitors in a manner similar to the positive power supplies. The
power connection V
should have a ceramic bypass capacitor to
the ground plane with short leads and decoupling components to
prevent resonance in the power leads.
The voltages of V
and V
decide the output signal levels. These
two pins can draw fast transient currents of up to 2A, so they
should be provided with an appropriate bypass capacitor located
next to the chip pins. A ceramic capacitor of up to 1.0μF may be
appropriate, with a series ferrite bead to prevent resonance in the
power supply lead coming to the capacitor. Pay particular attention
to minimizing trace lengths, current loop area and using sufficient
trace width to reduce inductance. Surface mount components are
highly recommended. Since the output impedance of this driver is
very low, in some cases it may be desirable to add a small series
resistance in series with the output signal to obtain better waveform
transitions at the load terminals. This will of course reduce the
output voltage slew rate at the terminals of a capacitive load.
Pay particular attention that parasitic couplings are minimized from
the output to the input signal terminals. The parasitic feedback may
cause oscillations or spurious waveform shapes on the edges of
signal transitions. Since the input operates with signals down to
1.2V even small coupled voltages may cause problems. Use of
a solid ground plane and good power and signal layout practices
will prevent this problem. Be careful that a circulating ground
return current from a capacitive load cannot react with common
inductance to cause noise voltages in the input logic circuitry.
V
DD
High side supply voltage.
V
SS
Low side supply voltage. V
is also connected to the IC substrate. It is required to connect to the most
negative potential of voltage supplies and powered-up first.
V
H
Supply voltage for P-channel output stage.
V
L
Supply voltage for N-channel output stage.
GND
Logic input ground reference.
OE
Output enable logic input. When OE is high, (V
+V
)/2 sets the threshold transition between logic level
high and low. When OE is low, all outputs are at high impedance. Keep OE low until IC powered up.
Logic input. Input logic high will cause the output to swing to V
H
. Input logic low will cause the output to swing
to V
L
. Keep all logic inputs low until IC powered up.
Output drivers
INA, INB,INC, IND
OUTA, OUTB, OUTC, OUTD
Substrate
The IC substrate is internally connected to the thermal pad. Thermal Pad and V
SS
must be connected
externally.
Pin Description
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