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參數(shù)資料
| 型號(hào)： | MD80C32-36SCD |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 36 MHz, MICROCONTROLLER, CDIP40 |
| 文件頁數(shù)： | 206/313頁 |
| 文件大?。?/td> | 4988K |
| 代理商： | MD80C32-36SCD |
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307
SAM9X25 [DATASHEET]
11054E–ATARM–10-Mar-2014
25.5.1 Arbitration Scheduling
Each arbiter has the ability to arbitrate between two or more different master requests. In order to avoid burst breaking
and also to provide the maximum throughput for slave interfaces, arbitration may only take place during the following
cycles:
1.
Idle Cycles: When a slave is not connected to any master or is connected to a master which is not currently
accessing it.
2.
Single Cycles: When a slave is currently doing a single access.
3.
End of Burst Cycles: When the current cycle is the last cycle of a burst transfer. For defined length burst, predicted
end of burst matches the size of the transfer but is managed differently for undefined length burst. See Section
4.
Slot Cycle Limit: When the slot cycle counter has reached the limit value indicating that the current master access
is too long and must be broken. See Section 25.5.1.2 “Slot Cycle Limit Arbitration”
25.5.1.1 Undefined Length Burst Arbitration
In order to prevent long AHB burst lengths that can lock the access to the slave for an excessive period of time, the user
can trigger the re-arbitration before the end of the incremental bursts. The re-arbitration period can be selected from the
following Undefined Length Burst Type (ULBT) possibilities:
1.
Unlimited: no predetermined end of burst is generated. This value enables 1-kbyte burst lengths.
2.
1-beat bursts: predetermined end of burst is generated at each single transfer during the INCR transfer.
3.
4-beat bursts: predetermined end of burst is generated at the end of each 4-beat boundary during INCR transfer.
4.
8-beat bursts: predetermined end of burst is generated at the end of each 8-beat boundary during INCR transfer.
5.
16-beat bursts: predetermined end of burst is generated at the end of each 16-beat boundary during INCR
transfer.
6.
32-beat bursts: predetermined end of burst is generated at the end of each 32-beat boundary during INCR
transfer.
7.
64-beat bursts: predetermined end of burst is generated at the end of each 64-beat boundary during INCR
transfer.
8.
128-beat bursts: predetermined end of burst is generated at the end of each 128-beat boundary during INCR
transfer.
Use of undefined length16-beat bursts, or less, is discouraged since this generally decreases significantly overall bus
bandwidth due to arbitration and slave latencies at each first access of a burst.
If the master does not permanently and continuously request the same slave or has an intrinsically limited average
throughput, the ULBT should be left at its default unlimited value, knowing that the AHB specification natively limits all
word bursts to 256 beats and double-word bursts to 128 beats because of its 1 Kbyte address boundaries.
Unless duly needed, the ULBT should be left at its default value of 0 for power saving.
This selection can be done through the ULBT field of the Master Configuration Registers (MATRIX_MCFG).
25.5.1.2 Slot Cycle Limit Arbitration
The Bus Matrix contains specific logic to break long accesses, such as back-to-back undefined length bursts or very long
bursts on a very slow slave (e.g., an external low speed memory). At each arbitration time a counter is loaded with the
value previously written in the SLOT_CYCLE field of the related Slave Configuration Register (MATRIX_SCFG) and
decreased at each clock cycle. When the counter elapses, the arbiter has the ability to re-arbitrate at the end of the
current AHB bus access cycle.
Unless a master has a very tight access latency constraint, which could lead to data overflow or underflow due to a badly
undersized internal FIFO with respect to its throughput, the Slot Cycle Limit should be disabled (SLOT_CYCLE = 0) or
set to its default maximum value in order not to inefficiently break long bursts performed by some Atmel masters.
However, the Slot Cycle Limit should not be disabled in the particular case of a master capable of accessing the slave by
performing back-to-back undefined length bursts shorter than the number of ULBT beats with no Idle cycle in between,
since in this case the arbitration could be frozen all along the burst sequence.
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