參數(shù)資料
型號: MD80C52CXXX-25SCD
廠商: TEMIC SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 25 MHz, MICROCONTROLLER, CDIP40
文件頁數(shù): 65/145頁
文件大?。?/td> 22337K
代理商: MD80C52CXXX-25SCD
157
XMEGA C3 [DATASHEET]
8492F–AVR–07/2013
Table 33-145.Two-wire interface characteristics.
Notes:
1.
Required only for f
SCL > 100kHz.
2.
C
b = Capacitance of one bus line in pF.
3.
f
PER = Peripheral clock frequency.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
VIH
Input high voltage
0.7*VCC
VCC+0.5
V
IL
Input low voltage
-0.5
0.3*V
CC
V
hys
Hysteresis of Schmitt trigger inputs
0.05V
CC
VOL
Output low voltage
3mA, sink current
0
0.4
tr
Rise time for both SDA and SCL
20+0.1Cb (1)(2)
300
ns
t
of
Output fall time from V
IHmin to VILmax
10pF < C
b < 400pF
20+0.1C
b
250
tSP
Spikes suppressed by input filter
0
50
II
Input current for each I/O Pin
0.1VCC < VI < 0.9VCC
-10
10
A
C
I
Capacitance for each I/O Pin
10
pF
fSCL
SCL clock frequency
fPER (3)>max(10fSCL, 250kHz)
0
400
kHz
RP
Value of pull-up resistor
f
SCL 100kHz
fSCL > 100kHz
tHD;STA
Hold time (repeated) START condition
f
SCL 100kHz
4.0
s
fSCL > 100kHz
0.6
t
LOW
Low period of SCL clock
fSCL 100kHz
4.7
f
SCL > 100kHz
1.3
t
HIGH
High period of SCL clock
f
SCL 100kHz
4.0
fSCL > 100kHz
0.6
tSU;STA
Set-up time for a repeated START
condition
f
SCL 100kHz
4.7
f
SCL > 100kHz
0.6
t
HD;DAT
Data hold time
fSCL 100kHz
0
3.45
s
f
SCL > 100kHz
0
0.9
t
SU;DAT
Data setup time
f
SCL 100kHz
250
fSCL > 100kHz
100
tSU;STO
Setup time for STOP condition
f
SCL 100kHz
4.0
f
SCL > 100kHz
0.6
t
BUF
Bus free time between a STOP and
START condition
fSCL 100kHz
4.7
f
SCL > 100kHz
1.3
V
CC
0.4V
3mA
----------------------------
100ns
C
b
---------------
300ns
C
b
---------------
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