77
ATtiny25/45/85 [DATASHEET]
2586Q–AVR–08/2013
Figure 11-13 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast PWM mode where
OCR0A is TOP.
Figure 11-13. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Prescaler (f
clk_I/O/8)
11.9
Register Description
11.9.1
GTCCR – General Timer/Counter Control Register
Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization Mode. In this mode, the value written to
PSR0 is kept, hence keeping the Prescaler Reset signal asserted. This ensures that the timer/counter is halted and
can be configured without the risk of advancing during configuration. When the TSM bit is written to zero, the PSR0
bit is cleared by hardware, and the timer/counter start counting.
Bit 0 – PSR0: Prescaler Reset Timer/Counter0
When this bit is one, the Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hard-
ware, except if the TSM bit is set.
11.9.2
TCCR0A – Timer/Counter Control Register A
Bits 7:6 – COM0A[1:0]: Compare Match Output A Mode
Bits 5:4 – COM0B[1:0]: Compare Match Output B Mode
The COM0A[1:0] and COM0B[1:0] bits control the behaviour of Output Compare pins OC0A and OC0B, respec-
tively. If any of the COM0A[1:0] bits are set, the OC0A output overrides the normal port functionality of the I/O pin it
is connected to. Similarly, if any of the COM0B[1:0] bits are set, the OC0B output overrides the normal port func-
tionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to
the OC0A and OC0B pins must be set in order to enable the output driver.
OCFnx
OCRnx
TCNTn
(CTC)
TOP
TOP - 1
TOP
BOTTOM
BOTTOM + 1
clk
I/O
clk
Tn
(clk
I/O/8)
Bit
7
6
5
4
3
2
1
0
TSM
PWM1B
COM1B1
COM1B0
FOC1B
FOC1A
PSR1
PSR0
GTCCR
Read/Write
R/W
R
R/W
Initial Value
0
Bit
7
6
5
4
3
210
COM0A1
COM0A0
COM0B1
COM0B0
––
WGM01
WGM00
TCCR0A
Read/Write
R/W
R
R/W
Initial Value
0